jtag: make debug arch defines local to jtag.c

Move debug arch defines to jtag.c since they aren't used anywhere else.
Also rename ARM_DEBUG_ARCH_V7_1 to ARM_DEBUG_ARCH_V7p1 to avoid clashes
with similar define in hw_breakpoint.h that is enabled when hardware
breakpoints are enabled.

Change-Id: I5f4b24b7aec50413f97a5b1854e6fadf2e4ab514
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
tracing: ftrace events for user faults and undefined instructions

New ftrace events (user_fault and undef_instr) for data, prefetch
or undefined instruction aborts. The new ftrace events are under
events/exception.

Change-Id: Iea328b71a1f623861cac9b45d858c3bbe09e1b82
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
coresight: A DLKM to abort trace on userspace abort

A DLKM to abort tracing on an user space data, prefetch or
undefined instruction abort.

Change-Id: Iaba14628601ea6d3649e05423f8570131eea39f7
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
coresight: use ETMPDCR instead of ETMCR for ETM power/clock control

Use ETMPDCR instead of ETMCR for ETM power/clock enable/disable. ETMPDCR
doesn't have corresponding cp14 access and hence will help with subsequent
multicore ETM support changes for 8974. ETMPDCR is available for PFTv1.1
and ETMv3.5 compliant ETM implementations.

Change-Id: I4b190b963cda29b406971cf075db36213b140495
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: move cp14.h to include/asm/hardware

Move cp14.h to include/asm/hardware so that it can be used by code
inside mach-msm as well as drivers/coresight.

Change-Id: I3f5cd6e1768378ec26abcd1e7328977836dce60f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: cp14 support for etm driver for krait v3

Use cp14 accesses to ETM registers for Krait v3 to avoid
limitations with memory mapped accesses.

Change-Id: Ia956eb0f5b45c748ffb5dd13dd14dc9595b9c68a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Revert "coresight: disable ETM probe for Krait v3"

This reverts commit 670627c323f1d6a72a35763d6b9dddca18f654df. We now
have cp14 based ETM support for Krait v3 so ETM tracing for Krait v3
can be turned on. This will enable ETM usage on Krait v3.

Change-Id: Ie7189c38d4aee43580ac145edceb8ffdbe8c9072
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: ignore multiple calls to coresight_abort

coresight_abort allows for abruptly stopping the current sink from
accepting new data hence avoiding polluting trace with information
after the point of interest.

Depending upon the call site, coresight_abort could end up getting
called more than once. This change will help with ignoring
subsequent calls to coresight_abort so that abort callback is
called just once. This is in line with treating abort as a one time
abrupt stop.

Change-Id: I634001e832ee7fa1b23f67698bd2d5dd12f8d65d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: initialize buf during tmc etr probe

Initialize buf for TMC ETR to the virtual address of the allocated
buffer memory. This will ensure a read on TMC ETR device node when ETF
is the current sink doesn't fail.

Change-Id: Id23dd9502ec728567c5b137354ca2d734f9309dc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: enable and disable STM during probe

Enable and disable STM during probe to undo the effect of RPM
temporarily turning on STM to ETF path. This ensures that all
the coresight components from STM to the default compile time
sink (ETF) get disabled in probe thereby resulting in their
states to more closely correspond to their reset states.

This is necessary since coresight drivers are designed to assume
reset state (on a power on boot) for the devices they control.

Change-Id: I8707f6134de2488754fb01b5e2830588efa729cc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: explicitly control ETMCR & preserve prog & power down bits

Explicitly clear and set ETMCR power down bit as part of the ETM
register programming sequence since if this bit is set, writes to
some registers and fields might be ignored.

Moreover, ETMCR prog and power down bits are not directly modifiable
via the sysfs based MODE selction code. Instead they can implicitly get
modified by other code. So always preserve their values while
enabling ETM trace since the ctrl is a shadow of ETMCR bits that
are only modifiable via the sysfs based MODE selection code.

Change-Id: I842a42acdafb112759a1787ec6fc41140812020d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: implement runtime pc save control

Add runtime control for enabling/disabling program counter save feature.
Enabling program counter save feature will enable pc to be saved on
reset but implies ETM being left powered on. So we provide user runtime
control to enable the feature when debugging or disable it while taking
power measurements.

Change-Id: Ib007da851ee7f3b0fac195da62aac7def68cc67a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
defconfig: build control_trace module for msm8960

set config item to build DLKM to abort tracing on a prefetch, data
or undefined instruction abort.

Change-Id: I6e12fc228ca2586a93c376c30cec9e347d627f1d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
coresight: Export coresight-stm header to userspace

Export coresight-stm header for userspace STM logging
definitions.

Change-Id: I75923ea8beea36269995e311c3fbb2667beac3cc
Signed-off-by: David Ng <dave@codeaurora.org>
coresight: Remove license info from coresight-stm.h

Remove license info from coresight-stm.h header file as it
is exported to userspace.

Change-Id: I49968e160fd2eb2e1499bb4c07b56676e9b280c6
Signed-off-by: David Ng <dave@codeaurora.org>
coresight: use 2K block size transfers for output via usb

For better throughput and to avoid limitations, use 2K block size
tranfers when outputting data over usb using ETR. Moreover, USB 3.0
currently only supports 2K block size for the descriptors.

Change-Id: Idc68c4d503e3ccca7715d3cbec21daedfbc2df6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: resolve pcsave and etm tracing concurreny issue

Always clear ETMCR[pwrdwn] while enabling trace. This is used as
a logic enable and is a pre-requisite while enabling trace. So
switch to an implementation that does this and removes the save
and restore for pwrdwn and pwrup.

Change-Id: I8a14efe8fd76368ed1e177a701013a504aa1876f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: graceful pcsave enable/disable for offline cores

Fail pcsave enable/disable if the core is offline so that it is
obvious to the user that the operation failed.

Change-Id: I2bd88636e1982a7de6b14f8b742d1f9bc7d23406
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: add STM support for explicit userspace entity ids

Add support to transport data sent using userspace library over
STM. Data stream will contain the entity id, protocol id and
options.

Change-Id: I5bd1810338fd13373bbad7de559765002c43c500
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: attempt to send data over STM only if size is non-zero

Send data over STM only if the data length specified is non-zero.
This will avoid potential issues while avoiding sending empty
packets.

Change-Id: I1792d4b342bdb8cae2c0a8edc2d2584b42c72f6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>