Supply BigInt constructors for Bits/UInt/SInt
Implement SInt/UInt order operators correctly

Before they converted the UInt operand to -2^n plus its value.
(How did this fall through the cracks for two years?)
Remove questionable Node => SInt conversion function
Remove isSigned property of Node

This notion presupposed that all types are integral, and it made the backend
logic more complex.  Signed operators like >> on SInt now are treated as
different operators entirely from their unsigned counterparts.
Remove > and >= operators from backends

They become < and <=, with the operands swapped, in the frontend.
Turn u%s and s%u operators into s%s under the hood

Before, we were emitting syntactically incorrect Verilog.
Update test cases to reflect removal of isSigned
Fix Mem with unconditional read enable

This also removes some old Mem-related cruft.
Dumping vcd before clock_hi is the most logical choice. Recall, the logic of clock_lo ensure that after its execution all signals are 'consistent' (ready to be clocked in, etc.) according to the current state and inputs whereas clock_hi just updates registers. This change is consistent with how the reference-chip testbench is constructed.
module c++ backend
allow multiple keys for is
merge
Fix width inference bug for UInt(1) << io.x

Bits.maxNum's implementation was dubious, and Node.maxNum seemed
to do the trick.  (That said, Node.maxNum should probably throw
an exception, and Bits.maxNum should be give Node.maxNum's old
implementation.  It doesn't make sense for Node to be an unsigned
integer by default.)
Make ROMs synthesizable; remove O(n^2) code

"initial" => "always @(*)"
String => StringBuilder
Fix Mux(cond, SInt, UInt)

But the Mux implementation is still super ghetto...
Clean up isLit/litOf tomfoolery
fix: update scct to 0.2.1 after 0.2 was removed from maven repo
add option to build with Maven3 - thanks Rupert
Improve Mux1H QoR

The previous implementation did not take advantage of the one-hot
property of the input, resulting in a priority encoder.

I also removed some redundant constructors (leveraging Vec <: Seq).
Improve PriorityEncoderOH QoR

Exposing a higher-level priority encoder structure improves QoR for
Synopsys DC, at least.  (It also results in fewer Chisel nodes.)