[FIX] Add missing definitions for xilinx platform in global.h

* Split _DEV_MICROBLAZE_ into big and little endian
[TASK] Add trace macros for PDO module
[TASK] Add bit-sized integer type macros
[TASK] Implement macro UNUSED_PARAMETER()

The macro is implemented as a cast to void. This should
work for all used compilers.
[FIX] Replace "winpcap" by "pcap library" in the CN console demo
[TASK] update Altera POWERLINK IP-Core to V0.2.7

* fix bug if PDI DPR is larger 2 kB
* enhance DMA master path to 32 bit address width
[TASK] update Xilinx POWERLINK IP-Core to V0.2.7

* fix bug if PDI DPR is larger 2 kB
* fix BRAM size to values of power 2
* enhance DMA master path to 32 bit address width
[TASK] update openMAC drivers to V0.2.7

* fix memory leak in omethlib
* fix sync-interrupt generation
* prepared for filling internal memory with functions
[FEATURE] Move functions from interrupt context to internal memory

* Introduce internal memory map categories for altera and xilinx and
  different optimization levels -> needs opt level makros during
  compile time!
* Move time critical functions to internal memory.
* Reduce optimization level to -O2 (needs less TCM with the same
  performance)
[TASK] update Altera directIO examples

The examples are recompiled with POWERLINK IP-Core V0.2.7.

note: SYSTEC_ECUcore-EP3C untested!
[TASK] update Xilinx directIO examples

Cleanup and set packet buffer higher 1 GB
[TASK] Revise MN asynchronous slot self-invitation

The MN only assigns the asynchronous slot to itself if the corresponding
asynchronous Tx buffer is ready. Hence, the invitation is not reverted within
the SoA packet buffer.
[FIX] Xilinx demo: 'make clean_hw' target can be called twice

* system.make file in the demo was removed and therefore it was not
  possible to call it again.
  -> system.make is now regenerated when the clean command is called!

* Also clean the SDK export folder when using make clean_hw
[TASK] Add eclipse project files to xilinx example

* This links all needed source files to the project and enables easier
  editing of the example. Also all make targets are available by default.
* Update xilinx documentation to fit to new project import.
* Add .gitignore file to xilinx demos
[FIX] Remove garbage at line 84 in global.h
[FIX] Remove TxEr signal in lx150t directIO designs

* The unconnected TxEr pin resulted in a bad routing and produced corrupted
  frames on the network.
* Uncomment timing requirements to improve timing
[TASK] introduced download-all command for Xilinx demo

The command 'make download-all' enables to download the bitstream and
the elf to the FPGA.
[FIX] EplNmtMnu: Always forward kEplNmtNodeEventFound to application

Previously, the kEplNmtNodeEventFound-Event (IdentResponse received) was
only forwarded to application at the very first time, but not after an
NMT ResetConfig or ResetNode command. This changes now, because the
application might be interested in all IdentResponses received.

If necessary in the future, the API could be extended to inform the
application about the internal state/reason for the IdentResponse.

Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
[FIX] timing issue with MII phy interface

Add register stage in RMII-TO-MII converter in rx and tx direction.
This aligns the bus signals, which reduces the bus-skew below 1 ns.
Note that this increases the response delay by additional 80 ns.
[FIX] Revise timing constraints of Xilinx examples

* relax MII phy timing to avoid metastability
* omit unused Tx Error pin