tracing: ftrace events for user faults and undefined instructions

New ftrace events (user_fault and undef_instr) for data, prefetch
or undefined instruction aborts. The new ftrace events are under
events/exception.

Change-Id: Iea328b71a1f623861cac9b45d858c3bbe09e1b82
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Perf: Restore correct CPU's PMU counters after power collpase

Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.

Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:

	arch/arm/kernel/perf_event.c
Perf: Make L1 PMU IRQ name target independent

Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.

Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add generic IRQ handlers for ARMv7 PMU's

For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.

Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Let platforms decide IRQ request methods.

This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.

Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.

The default behavior is maintained for all other ARM targets.

Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: Perf: Differentiate between L1 and L2 PMU IRQs

The L2 perf code shares some resource reservation functions
with the L1 perf code. In these functions, use defaults
only if they're not defined for the L1 and L2.

Change-Id: I5a390aa0085694466800db78b51837556aa12cdd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Assign proper routine to free IRQ

If the platform descriptor does not provide
its own free_irq function, default to the fallback
version.

Change-Id: I185186bf68b79e2dbfba77b0de66eb4daaf32fb8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's

The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.

Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/perf_debug.c
Perf: Toggle PMU IRQ when CPU's are hotplugged

When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.

Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:

	arch/arm/kernel/perf_event.c
	arch/arm/mach-msm/perf_debug.c