Perf: Check perf activity on correct CPU

The CPU hotplug notifier is not always preempt safe.
So relying on smp_processor_id() is not correct.

Use the cpu id from the notifier as the target
CPU to check for perf activity before hotplug or power
collapse.

CRs-Fixed: 454688
Change-Id: I1a96b236904a2c8ae2f82bbceab4ca8a195395d1
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>
Perf: Add DT support for L1 and L2 PMU

Add device tree bindings for L1 and L2 performance
monitoring units.

CRs-Fixed: 430010
Change-Id: Ia10e21a445e9daa6b2e4a3f1dba4881e3e7b2ccb
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>

Conflicts:
	arch/arm/mach-msm/perf_event_msm_pl310.c
Perf: Add cortex A5 device tree support

Support is already specified the 9625 device tree.
This adds it to the perf events subsystem.

CRs-fixed: 467815
Change-Id: I0a1dd642294247d79d5be06483b6a916ba32bbda
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>
Perf: Add L1 counters to tracepoints

Create a new tracepoint to get L1 PMU counter
information at every context switch. Counters
are captured only when the tracepoint is enabled
via perf or ftrace.

Change-Id: If05527b29e04c700170cfdf9f88d300b2f558ffa
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>
Perf: Add cortex A7 perf support

Support perf events for cortex-A7 PMU

Change-Id: Ie44b077d56f9b538e99ae675efaf1829c1b752b7
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: Hieu Phan <aznrice2k4@gmail.com>