various hdl: fix modelsim errors
hdl/sim/ddr_model/ddr3_model.v: Change module defines

We should change this approach to not become a conflict
between our values and the original ones
hdl/modules/*/acq_ddr3_iface.vhd: Aggregate data before sending

There were some problems with the previous simplistic approach
of sending the data to the DDR3 controller as soon as it arrives,
as we had to mask the most part of the bits and that incurred
a low throughput.

Now, we wait until we have the whole DDR word in order to send it
and have higher performance
hdl/testbench/*/wb_acq_core_test/verilog/*: update testbench