cores: adv_debug_sys: For X to zero during sim in crc module

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge pull request #12 from fjullien/for-upstream-new

cores: adv_debug_sys: Force X to zero during sim in crc module
Merge pull request #13 from skristiansson/for-openrisc

cores: updates fixes and additions
wb_avalon_bridge: wb burst to avalon pipeline access translation

Since there is no way of knowing what kind of (avalon) bursts
are suppported by the slaves we connect to, the wishbone bursts
are translated into avalon pipelined reads rather than avalon
bursts.
Wishbone allows for bursts to be ended at arbitrary cycles
(with the 'end burst' commmand), such cases are handled by
waiting out the remaining pending reads and filtering out the
readdatavalid signal from the wb_ack signal.