Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for the GHC calling convention.

This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185592 91177308-0d34-0410-b5e6-96231b3b80d8
Add MachineBasicBlock::addLiveIn().

This function adds a live-in physical register to an MBB and ensures
that it is copied to a virtual register immediately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185594 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be  scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185595 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.

These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r185595-185596 which broke buildbots.

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for futimens for platforms that don't support futimes.

Patch by pashev.igor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185601 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily revert 185601 as it caused cmake build regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185603 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r185601 with a fix for the cmake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185605 91177308-0d34-0410-b5e6-96231b3b80d8
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
Add a space between closing template '>' to unbreak build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185607 91177308-0d34-0410-b5e6-96231b3b80d8
Tabs to spaces. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185612 91177308-0d34-0410-b5e6-96231b3b80d8
Live-in copies go *after* EH_LABELs.

This will soon be tested by exception handling working at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185615 91177308-0d34-0410-b5e6-96231b3b80d8
FastISel can only apend to basic blocks.

Compute the insertion point from the end of the basic block instead of
skipping labels from the front.

This caused failures in landing pads when live-in copies where inserted
before instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185616 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify landing pad lowering.

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be  scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185617 91177308-0d34-0410-b5e6-96231b3b80d8
Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185618 91177308-0d34-0410-b5e6-96231b3b80d8
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.

These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
Supporting ssize_t on WIN64 with its proper size.  Patch thanks to David Cournapeau!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185627 91177308-0d34-0410-b5e6-96231b3b80d8
SimplifyCFG: Teach switch generation some patterns that instcombine forms.

This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Add asm parser support for CR expressions

This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8