Parameterize register widths based on number of strands per core
Make store buffer and load miss unit consider number of strands
Create a new 'multiplexer' class that takes a concatenated set of inputs. Remove a bunch of places
where the number of items was hard coded in inferred muxes.
Make the number of hardware threads per core a configuration parameter.  It can be changed by modifying the value of the STRANDS_PER_CORE define in defines.v.
There are a few small caveats:
- The direct test harness expects four strands and does not work correctly with other numbers
- The strand state statistics in the verilog simulator top is also hard coded for four strands