[CORE] move the load balancer to a specific directory.

This will allow to choose a particular load balancer when
more will be added.

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[DRIVERS] First-cut implementation of USB framework.

This patch adds first-cut implementation of USB framework.

USB is a complicated and very much needed framework because
of the range and diversity of devices available over USB bus.

This is still work in progress. More patches will follow.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Introduce vmm_spin_lock_irqsave_lite() API

We add new spin lock APIs which avoids preempt enable/disable
so that locking/unlocking does not depend on scheduler.

This new APIs are for very crucial modules which need to use
spin locks but need it to be faster.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] timer: Protect active event list on each host CPU

Timer events when started are always scheduled on current host CPU.

In case of SMP systems, the timer events may be stopped on-the-fly
from any other host CPU hence, we need to protect the active event
list on each host CPU.

This patch adds protection to active event list on each host CPU.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Save/restore ADFSR and AIFSR upon VCPU switch

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Fix save/restore of SP_fiq banked register

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] scheduler: Use lite spin lock API in vmm_scheduler_state_change()

The usual spin lock APIs call vmm_scheduler_preempt_disable()/enable()
hence, we use lite spin lock API in vmm_scheduler_state_change() to avoid
state changes depending on preempt enable/disable and also make state
changes little faster.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DOCS] Update design doc as-per latest code.

Signed-off-by: Anup Patel <anup@brainfault.org>
[LIBS] Fix bitmap_zero(), bitmap_fill(), and bitmap_copy()

We cannot use BIT_WORD() to determine number of longs. Instead, we should
be using BITS_TO_LONGS() to determine number of longs from number of bits.

This patch fixes above described issue in bitmap_zero(), bitmap_fill(),
and bitmap_copy() APIs.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Make d-cache operations by set/way SMP safe.

A arm32ve VCPU may be preempted when doing d-cache operations
by set/way and this VCPU might get scheduled on another host CPU
on a SMP host.

To handle this situation we trap d-cache operations by set/way
for arm32ve VCPU and flush the entire d-cache when scheduled
on another host CPU. We use per-VCPU cpumask to keep track of
host CPUs on which d-cache flush is pending and we fill this
cpumask with ones when we see a d-cache operation by set/way.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Optimize access to normal VCPU private context

This patch does few optimizations and restructures arm_priv_t to
speedup read/write to arm_priv_t and CP15 context.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Remove redundant per-guest stage2 ttbl lock

The LPAE MMU already implements spinlock based locking for ttbl
updates hence a per-guest stage2 ttbl lock is redundant.

This patch removes the redundant stage2 spinlock from per-guest
private context.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Fix return value of arch_spin_lock_check()

The arch_spin_lock_check() should return TRUE if spinlock is locked and
should return FALSE if spinlock is available.

This patch fixes the return value of arch_spin_lock_check() in arm32 and
arm32ve as-per above described semantics.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Re-organize struct vcpu and make it more SMP safe

This patch does number of changes to struct vcpu in-order to make
accesses to vcpu instances SMP safe in vmm_manager and vmm_scheduler.

Now we have two separate spinlocks to protect scheduler context and
load balancing context in a VCPU instance.

Also, the VCPU state is considered as part of scheduler context
of a VCPU instance hence VCPU state should be accessed only after
acquiring 'sched_lock' of VCPU instance.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] Implement pending FIXMEs in usb core framework.

This patch makes usb core framework more complete and reduces the
number of FIXMEs for pending code.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_vcpu_irq: fix ptr error handling

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[LIBS] kallsyms: export some more functions

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[CORE] Fix compile warning for 64-bit systems

Signed-off-by: Anup Patel <anup@brainfault.org>
[TESTS] Move SP804 timer code to basic test common code

This patch removes duplicate SP804 timer code from basic test of
all types of arm32 guests and adds common SP804 timer code in
common code.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TESTS] Rename basic test to basic firmware

Our basic test for arm32 guest is more than just a test code. It is more
of a firmware/bootloader for various arm32 guest hence, with this patch
we start referring basic test as basic firmware.

The changes done by this patch are as follows:
1. Rename "basic test" to "basic firmware" everywhere
2. Rename arm_test.bin to firmware.bin everywhere
3. Rename arm_test.elf to firmware.elf everywhere
4. Rename prompt from "arm-test#" to "basic#"

Signed-off-by: Anup Patel <anup@brainfault.org>