hdl/*/dbe_bpm_fmc516.ucf: no more CLOCK_DEDICATED_ROUTE constraints
emb-sw/dbe_main.c: disable adc ramp test
scripts/*: folder rearrangement and fpga programmer update
emb-sw/*/fmc516.c: change active board LED
hdl/*/wb_fmc516/*: rearrangement of some signals
hdl/*/fmc516_adc_clk.vhd: fix 2x clock output
hdl/*/top/*/dbe_bpm_fmc516.vhd: update top file
Merge branch 'wb-fmc516-devel' into dsp-devel

Conflicts:
	embedded-sw/dbe_main.c
	hdl/syn/loader/impact.batch
hdl/ip_cores/dsp-cores: update submodule reference
emb-sw/dbe_main.c: disable fmc516 ramp test
emb-sw/fmc/*: tune adc delays
hdl/*/fmc516/*: fix MMCM values for 112.5831 MHz input clock
hdl/*/dbe_bpm_dsp/*: small fixes, use 2x clock, add DSP debug signals
hdl/*/dbe_bpm_dsp/*: add sys_clk and clk200mhz constraints
hdl/*/dbe_bpm_dsp/*: add sample ADC acquisition
hdl/*/syn/dbe_bpm_dsp/*: update syn files
hdl/*/wb_fmc516/*: fix vcxo i2c missing scl_oe_n line
Merge branch 'wb-fmc516-devel' into dsp-devel
wb_fmc516/*: add ADC clock synch'ed reset