renamed examples/kc705 to examples/pcie-axi-scratchpad
Move Kintex7 boilerplate out of TopKC705
added pcie-echo example
was sending portal TLPs to the wrong fifo
added portal_mmap
added bluenoc mmap
fixed Makefile
removed generated echo code from pcie-axi-scratchpad
use 12 bit request ID to match zynq
updated echo with code generated by current version of bsvgen.py
Top of Echo PCIe design
bsvgen now adds mutually_exclusive attributes and uses a pulse wire to reduce bsc scheduler warnings
constraints file that defines the needed pcie clocks