making a breakout to test the driver and mosfet
added the pin-headers
initial layout
GND polygons for the gate driver
loaded Seeed DRU
autorouted
polygons on the mosfer high-current signals
make the signal back from drains to the driver normal instead of high-power
one more signal rename
one more signal rename
minor layout adjustments
I guess the huge grid would explain why routing failed...
a bit of manual routing, hoping it will help
switched to octagon pads to solve a clearance issue
route some more stuff manually first, adjust shape for symmetry
diffeent pin header part and 100mil spacing between pins
moved parts around a bit, put the bypass cap to gnd using vias
labels and optimizing size
adjusted mosfet position to allow for pin labels
actually if these are to be used together the pin aligment must match...