import unbound 1.4.17
MFprojects/camlock r248930:
Remove extra NULL checks. d_drv1 can never be NULL during periph life cycle.

MFC after:	2 weeks
MFprojects/camlock r248931:
Replace some direct mutex operations with wrappers.

MFC after:	2 weeks
MFprojects/camlock:
r249017:
Some cosmetic things:
 - Unify device to target insertion inside xpt_alloc_device() instead of
duplicating it three times.
 - Remove extra checks for empty lists of devices and targets on release
since zero refcount check also implies it.
 - Reformat code to reduce indentation.

r249103:
 - Add lock assertions to every point where reference counters are modified.
 - When reference counters are reaching zero, add assertions that there are
no children items left.
 - Add a bit more locking to the xptpdperiphtraverse().
Import ACPICA 20130328.
Merge ACPICA 20130328.
Add myself as a ports committer and my mentor relationship.

While in the repository, add myself to calendar.freebsd.

Approved by:	jpaetzel (mentor)
Adds security options to camcontrol this includes the ability to secure erase
disks such as SSD's

Adds the ability to run ATA commands via the SCSI ATA Pass-Through(16) comand

Reviewed by:	mav
Approved by:	pjd (mentor)
MFC after:	2 weeks
Use geom_uncompress here; we need this to fit in a 4MB flash part.
* Add AR9330/AR9331 to the soc identifier enum;
* Set it when probing the CPU type.
AR9330/AR9331 also needs to ACK the APB interrupt register, same as
AR724x.

This fixes 'stuck interrupt' problems I was having when writing the
uart interrupt code.
Implement the AR933x interrupt driven UART code.

* Enable RX and host interrupts during bus probe/attach
* Disable all interrupts (+ host ISR) during bus detach
* Enable TX DONE interrupt only when we start transmitting; clear it when
  we're done.
* The RX/TX FIFO depth is still conjecture on my part.  I'll fix this
  shortly.
* The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty"
  interrupt.  Sigh.  So..
* .. in ar933x_bus_transmit(), wait for the FIFO to drain before
  continuing.

I dislike having to wait for the FIFO to drain, alas.

Tested:

* Atheros AP121 board, AR9331 SoC.

TODO:

* RX/TX overflow, RX error, BREAK support, etc.
* Figure out the true RX/TX FIFO depth.
Now that interrupt driven uart IO is working, flip this back on.
Implement the AR933x ethernet support.

Obtained from:	OpenWRT
Add AP121 ethernet / switch PHY support.

* arge0 is MII
* arge1 is GMII
* the MDIO bus is on arge1, not arge0
* the default switch config is to have ports 0-3 as the switch group,
  with port 4 being an external PHY dedicated to arge0 (ie, 'cpu' port.)

Whilst I'm here, remove unused bits and pieces from the config.

Tested:

* AP121, ping on both arge0 and arge1
* Tested switch port detection using etherswitchcfg
Fix AR933x USB support - this needs the same controller initialisation
as the AR7242.

Tested:

* Atheros AP121, AR9331
* ZyDas wifi device, and 64MB (yes, ew) USB flash storage
Implement USB device reset and poweron.

Tested:

* Atheros AP131, AR9331 SoC
Add the basic GPIO pin mapping to the hints file.

Tested:

* AP121 board, tested USB/jumpstart LEDs
Print out DSISR in a fatal DSI trap.

Sponsored by:
HAL additions to enable MCI Bluetooth coexistence in the AR9300 HAL.

* Add the rest of the missing GPIO output mux types;
* Add in a new debug category;
* And a new MCI btcoex configuration option in ath_hal.ah_config

Obtained from:	Qualcomm Atheros