spi: zynq: Use standard numbering for qspi connection topology

is_dual, as per hw gui.
0 - single
1 - dual stacked
2 - dual parallel

Follow these number to in-sync with hardware gui flow.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Update the qspi dual parallel flash access logic

Updated the xilinx qspi dual parallel flash access support
to use 3-byte addressing instead of 4-byte addressing used
from the mtd flash layer.

Instead of sending 4-byte addressing from mtd layer and
then the controller will again divide the offset addr by 2 and
convert the 4-byte address into 3-byte address, With this
new logic the mtd will serve the offset as offset by 2 and
send the 3-byte addressing to controller driver, as the
driver is configured as separate bus with two mem the
controller internal hardware algorithm will take care the
dual parallel functionality.

Below are the changes for dual parallel to work:
- mtd layer -> addr/2, page_size*2, nr_sectors/nr_blocks*2
- driver -> enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Update the qspi dual stacked flash access logic

Updated the xilinx qspi dual stacked flash access.
Now the two memories were linearly accessable without
need a user interaction for selecting chip select.

Below are the changes for dual stacked to work:
- mtd layer -> nr_sectors/nr_blocks*2, update the U_PAGE flag
  when memory change happen.
- driver -> on LQSPI_CFG, Enable TWO_MEM[BIT:30] on LQSPI_CFG
  Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
  Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: zynq: Use divide by 8 baud rate for qspi dual stacked connection

Currently the qspi dual stacked support is available on afx boards,
there is a board hardware bug, that the controller will works on
divide by 8. hence changed the master mode baud rate divisor to /8
incase of dual stacked mode qspi.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Use spi_flash_read_common() in write status poll

Instead of using spi_xfer for SPI_XFER_BEGIN and SPI_XFER_END
separatley use common read call spi_flash_read_common() which
does the same.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Remove spi_flash_cmd_poll_bit()

There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Add Flag status reg polling support

Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.

Like polling for WIP(Write-In-Progress) bit n read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: spansion|stmicro|winbond: Update the dual qspi size logic

dual parallel:
	double the page_size and sector_size
dual_stacked:
	double the flash_size

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Sync the spi_flash_addr() changes w.r.t mainline code

Change the spi_flash_addr() logic based on the mainline code.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Use spi_flash_addr() in write call

Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Unify the bank handling logic

Unified the bank handling logic, placed in spi_flash_bank()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Fix address handling in dual parallel connection mode

Address in dual parallel mode needs to divide by 2 and then pass
to the controller interms of 3-byte addressing cmds.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Fix the read bank boundary for dual parallel

In dual parallel case the read boundary should be twise the
boundary that shoud use on the single/dual stacked case.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Remove unnecessary idcode0 arg in spi_flash_cmd_bankaddr_read|write()

idcode0 is stored in flash->idcode0 at probe time, hence removed
unnecessary idcode0 arg in spi_flash_cmd_bankaddr_read|write()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Use proper messages on printf

Used proper messages on printf() calls

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: zynq: Use enum members for is_dual status

Used enum members for is_dual status instead of numericals.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Define is_dual variable in erase/program/read

Use is_dual variable and assign flash->spi->is_dual value
instead of deferring the structure every time.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
zynq: qspi: Rename zynq_qspips.c to zynq_qspi.c

Remove ps suffix, which is not a mandatory and use simple
filename before pushing mainline.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
zynq: qspi: Rename few names

Use proper name for the driver before we go to mainline.
- XQSPIPS -> ZYNQ_QSPI
- NORM_READ -> NR
- FAST_READ -> FR
- DUAL_READ -> DR
- QUAD_READ -> QR
- ERASE_SUS -> ES
- ERASE_RES -> ER
- xqspips -> zynq_qspi
- zynq_spi_slave -> zynq_qspi_slave

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
zynq: qspi: Update driver description

Updated the driver description on header.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>