<rdar://problem/13384282> 

As much as I hate to leave this hacky code in that adds some d and q registers to ARM registers, I must leave it in.

The code is now fixed to not just assume ANY arm target will have registers in a certain order. We now verify the common regs are the same name and byte size before adding the d and q regs.



git-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@176752 91177308-0d34-0410-b5e6-96231b3b80d8
Remove my print statements I was using for debugging.



git-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@176753 91177308-0d34-0410-b5e6-96231b3b80d8