Formatted the documentation for host.py
DESIGN CHANGE! master only accesses 32-bit memory

Before the memory access with byte aligned. Now the memory access is
only 32-bit aligned. This simplifies calculations for the host and any
peripheral that needs to interact with the memory peripheral directly
DESIGN CHANGE/BUG FIX: Spcification Change/Data Loss

Memory is now accesssed through a 32-bit address mode instead of a byte
address interface. This simplifies transactions with the host and
modules that access the memory directly.

The bug fixes is specific to the case where the user writes in a
discontinuous fashion to the memory. So instead of writing to ALL of the
memory data is written a small amount at a time. The write stack was
intermittently dropping data. This was associated with counting. I've
observed that I have more consistent results when I implement a
'counting up' approach as apposed to count down to zero. Not only do I
need to implement less checks (to see if the count is at 1 or 0) it will
requrie less resources in the FPGA to implement counting as apposed to
subtraction
BUG FIX: Debugging the I2S core

Lots of very small changes that has led to actually listening to clear
music from one channel.

Theoretically the implemented changes should solve these issues and two
channels will be played afterwards!