[ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to
parse an identifier.  Otherwise, parseExpression may parse multiple tokens,
which makes it impossible to properly compute an immediate displacement.
An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in
the below example:

 __asm mov eax, [Symbol + ImmDisp]

The existing test cases exercise this patch.
rdar://13611297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179115 91177308-0d34-0410-b5e6-96231b3b80d8
Make check depend on all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179116 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for bottom-up SLP vectorization infrastructure.

This commit adds the infrastructure for performing bottom-up SLP vectorization (and other optimizations) on parallel computations.
The infrastructure has three potential users:

  1. The loop vectorizer needs to be able to vectorize AOS data structures such as (sum += A[i] + A[i+1]).

  2. The BB-vectorizer needs this infrastructure for bottom-up SLP vectorization, because bottom-up vectorization is faster to compute.

  3. A loop-roller needs to be able to analyze consecutive chains and roll them into a loop, in order to reduce code size. A loop roller does not need to create vector instructions, and this infrastructure separates the chain analysis from the vectorization.

This patch also includes a simple (100 LOC) bottom up SLP vectorizer that uses the infrastructure, and can vectorize this code:

void SAXPY(int *x, int *y, int a, int i) {
  x[i]   = a * x[i]   + y[i];
  x[i+1] = a * x[i+1] + y[i+1];
  x[i+2] = a * x[i+2] + y[i+2];
  x[i+3] = a * x[i+3] + y[i+3];
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179117 91177308-0d34-0410-b5e6-96231b3b80d8
This patch enables llvm to switch between compiling for mips32/mips64 
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info, 
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
Rationalize the formatting of these case labels. Having two sorted
columns is essentially impossible to edit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179119 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r179115 as it looks to have killed the ASan tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179120 91177308-0d34-0410-b5e6-96231b3b80d8
Update the version of dwarf we say we're emitting to at least 3.

Deals with a dwarf2 -> dwarf3 DW_FORM_ref_addr change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179122 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused method and default values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179124 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179125 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179129 91177308-0d34-0410-b5e6-96231b3b80d8
Fix some comment typos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179132 91177308-0d34-0410-b5e6-96231b3b80d8
Allow PPC B and BLR to be if-converted into some predicated forms

This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).

At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
Mips specific inline asm operand modifier 'D' 

Modifier 'D' is to use the second word of a double integer.

We had previously implemented the pure register varient of 
the modifier and this patch implements the memory reference.



#include "stdio.h"

int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
    int i;
    
    // The first word. Notice, no 'D'
    {asm (
    "lw    %0,%1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);

    // The second word
    {asm (
    "lw    %0,%D1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
Generalize the PassConfig API and remove addFinalizeRegAlloc().

The target hooks are getting out of hand. What does it mean to run
before or after regalloc anyway? Allowing either Pass* or AnalysisID
pass identification should make it much easier for targets to use the
substitutePass and insertPass APIs, and create less need for badly
named target hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179140 91177308-0d34-0410-b5e6-96231b3b80d8
__sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not in
xmm0 / xmm1.

rdar://13599493


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
Include the more specific header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179146 91177308-0d34-0410-b5e6-96231b3b80d8
Template the MachO types over endianness.

For now they are still only used as little endian.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179147 91177308-0d34-0410-b5e6-96231b3b80d8
PPC: Prep for if conversion of bctr[l]

This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
  void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
        ...
        beq 0, .LBB0_2
        std 2, 40(1)
        mr 12, 4
        ld 3, 0(4)
        ld 11, 16(4)
        ld 2, 8(4)
        mtctr 3
        bctrl
        ld 2, 40(1)
.LBB0_2:
        ...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
RegionInfo: Add helpers to replace entry/exit recursively

Contributed by: Star Tan <tanmx_star@yeah.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179157 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup PPCInstrInfo::DefinesPredicate

Implement suggestions made by Bill Schmidt in post-commit review. Thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179162 91177308-0d34-0410-b5e6-96231b3b80d8