Cpld optimizations

Here now all the optimizations I did during adapting the code to CoolRunner II CPLD.

In assume also your FPGA-implementation will show reduced logic usage without any loss in functionality.
I would be very much interested whether you can confirm it (and how much is the saving in case of PFGA).

Please let me know if you have any questions or find any issues with my changes.

You can find my testbench and project setup (still) at https://github.com/sd2k9/hdl_uart_echo

Cheers!

PS: It seems that this pull request also includes the one I made before ...