"wb_fmc516/*: all data chains are clocked with a single bufg clock"

In this way, we can transmit the raw adc data through all FPGA logic,
safely. Be aware though, that one must be careful with this simple
"trick". If the driving clocks are too different, in frequency, from
one another we could have some inconsistencies. This, however, should
not be the case as, by default, we work with the same clocks
for all channels (chains).