msm_fb: Disable LCDC/DSI Video timing generator during boot up

Disable LCDC and DSI Video timing generator during MDP
initialization if continuous splash screen is disabled.

Change-Id: I64276550f28e1f316c420f9cb158f7b8e938b8ea
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: Avoid multiple disable calls for vsync interrupt

For LCDC and DSI Video mode panels, there seem to be multiple
disable calls for Vsync interrupt term. Change to avoid this
issue by proper synchronization of vsync term and DMA term.

Change-Id: Iaf11ba92cc7db55c6196add2d7dea581cb29fc8a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: Handle histogram IRQ cleanly during suspend/resume

Currently, if the histogram disable IOCTL comes after panel
is turned off, we early return the IOCTL causing the interrupt
to be left enabled. This causes IPC issues during suspend. Fix
this issue by properly enabling/disabling the histogram interrupt
during suspend/resume scenario.

Change-Id: I4d38776a43ea854aff3c10c8d9d5450af1d98c91
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb : display : Block RGB downscale in MDP 4.0 and 4.1

Downscale is not allowed on RGB pipes in MDP 4.0 and 4.1. Hence,
fail the OVERLAY_SET ioctl for such configurations.

Signed-off-by: Pradeep Jilagam <pjilagam@codeaurora.org>
(cherry picked from commit 3545573720822ce97ec37586f10fdf74a6d4f090)

Change-Id: I8445c18ac21cb7322eb9eb4c802623df5da07eb7
Signed-off-by: Gopal Goberu <ggober@codeaurora.org>
msm_fb: Release semaphore when display Unblank fails

When continuous splash is enabled, the display subsystem will be
turned on during first pan display after boot up. During this
process, we acquire a semaphore. Release the semaphore if display
init fails and the function has to return early.

CRs-fixed: 441973
Change-Id: I4c8ba0b5e7710a6f3d409be619d5014b3ee32e5b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: display: add fput_light to frame buffer

Frame buffer's (fb0) ref_count's need to be balanced. overlay_play()
increases fb0's ref_count (fget_light). This patch will decrease fb0's
ref_count by calling fput_light after commit.

Change-Id: I352da1fce99b344c059f615a6fe88cc6e7387d89
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
Signed-off-by: Iliyan Malchev <malchev@google.com>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm_fb: dsiplay: fix frame buffer f_count leak

Frame buffer maintains a reference count (f_count) which increased
by fget() and decreased by fput(). overlay play will apply
fget() to frame buffer if it was the soruce buffer and fput()
will be applied to it after pipe commit done. However there has
extra fput() apply to frame buffer at the time pipe is freed.
This patch fix the problem by  clear MDP_MEMORY_ID_TYPE_FB from
pipe's flags to avoid extra fput() applying to frame buffer.

CRs-fixed: 411394
Change-Id: Ib2b72e6277480b5ace23cda554be485d9d477b3d
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm_fb: Display: Fix Dithering issue for rgb565 format

Using RGB888 as source format and rgb565 as destination pixel format,
will cause image corruption on the display. Fix this issue by
setting the destination format as RGB888 in MDP and DSI controller
pixel format as RGB565 for DSI specific panels.

CRs-Fixed: 377484
Change-Id: If58976ee9cd4825efb39437170e54796fa2213e0
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm_fb: display: Enable scaling bit while setting x-flip bit

To enable left-right flip x-scaling bit should be set for
MDP 4.2 and above versions. This fixes the issue when RGB layer
pipes are not properly rotated.

Change-Id: I0afae4aecde39ce3ac4dcbefc0bda93510e7d18a
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm: mdp: Remove mixer1 blt for external

BLT mode is not needed for external displays since
there is no extra downscaling needed for videos.
msm_fb: display: silent blending error warning message

If there had no any pipe blending stage changes, then do not
call belnding set up to avoid unnecessary warning messges.

CRs-fixed: 467556
Change-Id: I07520b3b0917375c41405e736dcb9eb8a3daddc1
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm_fb: Fix adb shell start/stop issue when bypass enabled

Currently when 2/3/4 layer bypass is enabled, doing a adb shell
stop/start is failing overlay and composition happens through
GPU. Fix this issue by proper overlay configuration during this
scenario.

Change-Id: Ia04f1839bf80ed552671e48445af63a4dcd6bdfd
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: display: fix the hang issue caused by solidfill pipe

When mdp pipe solidfill mode is disabled, the staled pipe info is used
to update mdp pipe regs. This caused mdp hang. Since
mdp4_overlay_rgb_setup function already resets solidfill mode, this
patch removes any pipe register updates that are related to disabling
solidfill mode.

CRs-fixed: 467555
Change-Id: I23f4b29731c9097ab0cc38baa00cd35bc536d2ba
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm_fb: call the backlight control before FB_BLANK_POWERDOWN

You might see the white line while lcd off. You should turn lcd backlight
off before lcd off to avoid that issue. So call the notifier for backlight
before handling of FB_BLANK_POWERDOWN in msm_fb.

Change-Id: I3bd08025a949ec02a1fba7cef98a13d8977c135b
msm_fb: display: Program source address registers correctly

Scale filter FIR uses the adjacent pixels as part of the
processing. Source address registers should be program such that
they point to the first valid pixel so that non-ROI pixels are
ignored. This is done by making source x,y offsets to zero and
adding the computed offset to source address.

CRs-Fixed: 380020
Change-Id: I998fdd46f39dc67f32c422ec209da59d1add2e95
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay.c

Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Signed-off-by: lakshmi narayana p <lpatib@codeaurora.org>
msm_fb: display: add checking y direction for alpha drop

Alpha is dropped when scaling with non repeat pixel method.
Both x and y direction of scaling need to be cehcked for
alpha dropped.

(cherry picked from commit f0d08071a4e97c9018b8e8def498e07720201da8)

Change-Id: I69b8969c878f8422efecea86f93749e0970b77bc
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
video: msm: Clear previous histogram data on next startup

Clear the pointer to the userspace histogram struct when histogram is
started. Previously, when the histogram was stopped while a histogram read
was in progress, the pointer was not cleared, causing the next histogram
read to think that someone was already using the histogram.

CRs-Fixed: 361640
Change-Id: If09017149e98b35c49603372c554aa4c97f2de82
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
(cherry picked from commit 19e4b71f617e307cacf0be077e08bec5c37df290)
video: msm: Enable mdp clock for histogram and histLUT

Enable the mdp clock for histogram and histogram LUT to ensure that the
clock remains enabled when they are being accessed.

Change-Id: Ic744f2ee96b64442f23ba19aa1c38552c0dad83a
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
(cherry picked from commit e782ceab26e38590cd49a9bb273da1dbf1984ccd)
video: msm: Do not use disable_irq in the spin_lock_irqsave context

Both mdp_isr() and mdp_histogram_disable() uses the same
spin lock mdp_spin_lock variable.  One core waits for disabling
mdp_isr after acquiring mdp_spin_lock and other core in mdp_isr()
waits for spin lock mdp_spin_lock and dead lock between two cores.

Change-Id: I73a10494ab78e92fc88a348aed4f526091b51f89
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
(cherry picked from commit 946ca6389b8f8c70b62a2f1ab4d81b475395f7d8)
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
msm_fb: display: Evenly balancing load on MDP ports

Moving RGB1 and RGB2 to AXI port 1. This fixes underrun issues seen
on External display while connecting and disconnecting HDMI. This patch
evenly balancing pipe loads on each port.

Change-Id: I2dc1166d04bb938f9e233a6de52f1a8a3fdd29e2
CRs-Fixed: 435458
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>