dvisampler/datacapture: swap bit pairs
dvisampler: add RawDVISampler
dvisampler/decoding: hold C when DE=1
dvisampler: add sync polarity detection module (thanks Lars for suggestions)
dvisampler/resdetection: use DE instead of hsync
software/videomixer: use new resdetection regs
dvisampler/chansync: fix FIFO width
dvisampler: connect sync polarity detection
tb: add chansync
chansync: bugfix
build.py: support single DVI sampler
build.py: LOC clock generator components to limit breakage of the ISE shitware