Reduce number of z-buffer glitches when polygons are rendered as lines.
Added a second port to SCB_DDR, and created another AXI bus. Hooked hline_pcore to P1. Works...I'm surprised.
P0 has 75% more time than P1 by our priority timescheme.
Visible speedup on wasd elevator despite inefficient read/write of pcore...or maybe it's placebo.
Revert hline pcore to length 256 burst read. Functionally correct, and 2x speedup.
NEXT: Variable length burst read/writes for non-256 length line segments.