Merge pull request #29 from crpalmer/cm-10.2

Cm 10.2 video changes from the m7 kernel
board-msm8x60.c isn't being used, delete it to avoid merge conflicts
monarudo: removed unused driving params
msm_fb: HDMI: Update HPD logic to address HDMI PLL related issues

In the current implementation, the regulators pertaining to the
HDMI core are turned off/on as part of the configuration of the
HDP circuitry. As a result, the regulator that powers the HDMI
PLL is turned off before the HDMI clocks on the PLL are disabled.
This might lead to the PLL not getting locked when it is re-enabled.

This change turns on and off the regulators and clocks in proper
sequence.

CRs-Fixed: 360135
CRs-Fixed: 358598
Change-Id: Ie3630b543e78e83dc565edc32239935135ca4ca5
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/board-8064-display.c
	arch/arm/mach-msm/board-8930-display.c
	arch/arm/mach-msm/board-8960-display.c
	arch/arm/mach-msm/board-msm8x60.c
	arch/arm/mach-msm/clock-dss-8960.c
	drivers/video/msm/hdmi_msm.c

It looks like HTC partially implemented this same fix
msm_fb: hdmi: Break infinite loop

Currently, if HDMI PLL lock fails, it will retry. It retries until
the PLL is locked. This may result in infinite loop. This change will
limit the retries to max 10.

Change-Id: I1745643cba7bbc5272f1252208759a83258e9fcb
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm_fb: HDMI: Fix handling of HDMI PLL software reset

Whenever a software reset is asserted on the HDMI PLL, we should
wait for short time to wait for the PLL calibration to be
successful before checking to see if the PLL is locked.

CRs-Fixed: 378044
Change-Id: I736e2eff4dce778ba3e305d9461cdedc607156ae
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: clock-8960: Move DSI resets functionality to their own clocks

The DSI core resets are currently associated with the DSI byte clocks
because the DSI core clocks are managed by the DSI driver directly,
not the clock driver. Move the reset functionality out of the byte
and into their own reset-only branch clocks so that the footswitch
driver, which needs to assert these resets, can do so without
involving the unrelated byte clock.

Change-Id: I2b67ebc6eca343b853f441203874230b8e35f048
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: footswitch-8x60: Reset DSI domain along with MDP collapse/restore

Some DSI-related logic lives in MDP's collapsible GDHS domain for
8960, 8064 and 8930. Assert the reset to this domain when the reset
of MDP is reset. Use of the reset-only clocks added here assumes the
display driver is making sure the DSI clocks (not managed by the
clock driver) are enabled for the duration of the collapse and
restore sequences so that the resets propagate.

Change-Id: I18638624f7ac92b9cb7228b014df7a187fe974fb
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/devices-8930.c