working on folding the core functions and other improvements.

	modified:   examples/board_fignition/FIGsimavr.c
	modified:   simavr/sim/sim_fast_core.c
tweaks and bug fixes...

discovered erroneous side effect with setting sreg.
few errors in handling flags.
some ommisions with flag handling found in main core...  needs bugfix upstream.
some common instruction sequences folded together.

	modified:   simavr/sim/sim_avr.c
	modified:   simavr/sim/sim_core.c
	modified:   simavr/sim/sim_fast_core.c
polluted repository...  don't know how.  fixed.

	deleted:    examples/board_hd77480/run.lst (copy).sc
	deleted:    examples/board_hd77480/run.lst.diff
	deleted:    examples/board_hd77480/run.lst.fc
	deleted:    examples/board_hd77480/run.lst.sc
	deleted:    simavr/sim/sim_avr.h.orig
	deleted:    simavr/sim/sim_core.c.orig
	deleted:    simavr/sim/sim_elf.c.orig
Refactor ram read/write access funcitons to specifically favor ram access...
access faults and io handled together as speed penalty not as noticable.

	modified:   simavr/sim/sim_fast_core.c
true 16 bit push/pop functions...

	modified:   simavr/sim/sim_fast_core.c
more combining of operations...

pop/push now handles 16 bit instances.
lds/sts now handle double (16 bit) fetch/store.
miscelaneous cleanup.

	modified:   simavr/sim/sim_fast_core.c
io passed directly to handler...

previously io went through ram read/write handers...  no need.
known io operations now go directly to reg_io read/write handlers.

	modified:   simavr/sim/sim_fast_core.c
correction with push/pop...

accidentally used d5, evident when not combining...  error.

	modified:   simavr/sim/sim_fast_core.c
fast core reworked...

changed inst and uinst implementation.
moved combining instructions to individual relavent instruction.
ability to do read-modify-write.
more instructions combined.

	modified:   sim_fast_core.c
Merge branch 'master' of https://github.com/buserror-uk/simavr into fast-core-testing

Conflicts:
	simavr/sim/sim_avr.c

	modified:   simavr/sim/avr_uart.c
	modified:   simavr/sim/sim_avr.c
	modified:   simavr/sim/sim_avr.h
	modified:   simavr/sim/sim_elf.c
more combined instructions.
option for using multiplication to reduce or eliminate branching in branch instructions.
option for using shifting to reduce or eliminate branching in skip instructions.
option for using read-modify-write style operations with registers
some instructions simplified.
some miscelaneous core cleanup.

	modified:   simavr/sim/sim_fast_core.c
changed data types usage to Xint_fastXX_t types.

	modified:   simavr/sim/sim_fast_core.c
added cast to branch instruction.

	modified:   simavr/sim/sim_fast_core.c
a few extra instruction combinations added.

	modified:   simavr/sim/sim_fast_core.c
core cleanups and fixes...

macro: new_pc[0]=x --> NEW_PC(x)
macro: cycle[0]=x CYCLES(X)
improvements on CORE_FAST_CORE_DIFF_TRACE output.
added some documentation of option flags.
use of common data reference on some register access operations.
changes to allow core to operate local to project.
global uflash access option.
asr: calculate and use common negative result across flags.
moved a few bit shifts earlier in some functions, to reduce a few
	redundant operations.
std_std: operation fixes.
avr_core_run_many: tightened up the code a bit.
sim_fast_core_init: added to enable use local to project.

	modified:   simavr/sim/sim_fast_core.c
sim_avr.c: few changes here too...

	modified:   simavr/sim/sim_avr.c
Merge branch 'master' of https://github.com/buserror-uk/simavr into fast-core-testing
Latest changes for fast core ready for testing...

all pc and cycle updates moved to instruction handlers.
call handlers removed, cached opcodes now decoded in handlers.
instruction decoding and caching now in instruction translator functions.
extensive work diff tracing output.
run core loop reworked - sreamlined.
preparation for possible software pipelining in future.
more work eliminating if/else/branching code blocks.
more instructions simplified via extra handlers.
load/store with known non-io access moved to faster handlers.

	modified:   simavr/sim/sim_fast_core.c
Merge branch 'fast-core-testing' into board_fignition