mmc: dw-mmc: support DesignWare MMC Controller

This patch is supported DesginWare MMC Controller.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
EXYNOS: clock: add the get_mmc_clk function

To get more exactly sclk value, used the get_mmc_clk.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
EXYNOS: mmc: support DesignWare Controller for Samsung-SoC

Support DesignWare MMC Controller for Samsung Specific.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
mmc: dw-mmc: add dw-mmc's confiuration at Makefile

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
board: samsung: Add support of Arndale board

Arndale board is based on the Exynos5250 Soc. This patch
adds support for booting from mmc card

Signed-off-by: Girish K S <ks.giri@samsung.com>
board: samsung: Removed the hardcode clock values

Boards based on same Soc can you different clock values
so the values are moved to config file.

Signed-off-by: Girish K S <ks.giri@samsung.com)>
board: samsung: Added dwmmc initialization

EVT1 version of Exynos5250 has dwmmc controller.
This patch removes the Evt0 Init and replaces it with
the EVT1 dwmmc init

Signed-off-by: Girish K S <ks.giri@samsung)>
exynos: uart: s5p: fix the garbled decompressing linux...message

Fix the garbled decompressing linux...message and by enabling the uart
tx/rx fifo. Now that fifo is enabled, the uart read/write functions
are modfied to check the UFSTAT register for fifo status instead of
UTRSTAT (as required with fifo's enabled).

BUG=none
TEST=booted on daisy, Uncompressing Linux is fine

Change-Id: I2d4cccfc308483b15725f36babefc0b3203ec7d8
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/22260
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
arm: exynos: additional changes to arndale

added more changes to the configuration and clock of mmc

Signed-off-by: Girish K S <girish@avatar.(none)>
arm: exynos: fix issue in clock and pinmux

clock: the mmc get clock api return the clock value without
dividing the sclk by value of clk_sel register. The divider
value calculated in the dw_mmc driver for clk_div is wrong.
This patch adds the divider to fix the issue.

pinmux: The initialization of the sd_cdn pin was ignored, This
patch adds the selection and initialization of the early pin
state.

Signed-off-by: Girish K S <iks.giri@samsung.com>
driver: dwmmc: Add the clock divider code for exynos dwmmc

The exynos dwmmc Ip has 2 stage divider. The first divider
Register is in the vendor specific region of the dwmmc core
(CLK_SEL), and second is part of the dwmmc generic registers
(CLK_DIV).
The goal of this patch is to maintain a 100MHz clock output
before dividing it further by using the CLK_DIV.
Depending on the card enumeration, it can be further divided
by writing a correct divider in the dwmmc CLK_DIV register.

Signed-off-by: Girish K S <ks.giri@samsung.com>
The exynos dwmmc Ip has 2 stage divider. The first divider Register is in the vendor specific region of the dwmmc core (CLK_SEL), and second is part of the dwmmc generic registers (CLK_DIV). The goal of this patch is to maintain a 100MHz clock output before dividing it further by using the CLK_DIV. Depending on the card enumeration, it can be further divided by writing a correct divider in the dwmmc CLK_DIV register.

Signed-off-by: Girish K S <ks.giri@samsung.com>
DRIVERS: USB: Initialize HSIC PHYs and enable network support

Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
controller, connected to HSIC Phy of USB host controller via USB3503 hub.

This patch initializes the HSIC PHYs, performs reset sequence for USB3503
hub and enables the relevant config options for network to work.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Enable the signal for PSHOLD port
Added support for DHCP, PXE for Arndale board
arndale5250: Boot in Hyp mode and enable architected timers

First, to boot in Hyp mode we need to change to non-secure mode, which
involves configuring the frequency of the arch. timers and setting all
interrupts on the gic to group 1 (this code was inspired by the boot
wrapper code).

Second, signal the secondary CPU while still in secure mode and have the
secondary CPU run the SPL.  The SPL checks the hardware cpu id, and if
it's a secondary CPU, it will initialize non-secure mode inside the SPL,
enter Hyp mode, and finally enter a new SMP pen with the same poking stick
interface as the regular kernel uses.

Third, on CPU0 we wait until u-boot is fully up to actually enter the
non-secure mode on CPU0, and stay in non-secure svc mode right up until
we actually load the kernel, where the last thing we do is enter Hyp
mode.

Let it roll...

Signed-off-by: Jeremy C. Andrus <jeremya@cs.columbia.edu>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>