Fix for the bit train error probe register being only 1-bit wide.

The 4-bit error values were being driven through a 1-bit wide register
so the error values may have been mis-reported. Not sure why the Xilinx
tools do not issue errors in these cases, very annoying!
If enabled, the QDR is reset until the fabric and sys_clk MMCM's are locked.

This feature can currently be enabled by setting the QDR_MMCM_LOCK_EN environment
variable to something. It is not on by default because not all ADC's presently
break-out their MMCM locked signals. Eventually this feature should be enabled
via a checkbox in the QDR's yellow block mask.

Also in this commit I've broken the aux_clk MMCM locked signal in case it
is used as the fabric clock.
[adc5g] Changed MMCM locked signal in MHS to be consistent with @6d89bb1.
Added a "hard" reset line to QDR config.

This reset holds QDR reset high until it is de-asserted again by the OPB.
A normal "soft" reset can still be done by writing a 1 to offset 0 but if a
"hard" reset is needed this can be done by writing 256 to offset 0 instead.
Just be sure to write a 0 after that.
[QDR] Added "&& !cal_fail" to the PHY output mux.

Now if bit alignment fails instead of connecting the outputs (addr, read/write
enable, write data, etc) to the burst alignment logic which will not be started,
the PHY instead defaults to connecting the user logic to the QDR.

This has the benefit of being able to still read/write from the QDR's even
though calibration fails (which it has been for various frequencies).
Merge remote-tracking branch 'ska-sa/master' into crowley
Added an option to use 100 MHz REFCLK for IDELAYCTRL in roach_infrastructure.v.

By default roach_infrastructure will use the 200 MHz sys_clk-derived clock for REFCLK
as it normally would however when the environment variable IDCTRL_100 is set the core
will use 100 MHz instead. This is of course a non-Xilinx-approved clock rate but may
nevertheless solve QDR calibration failures at fabrics rates lower than 200 MHz. It
definitely works for 143 MHz (the SMA wideband correlator phase-I rate).

USE this feature AT YOUR OWN RISK.
[adc5g] Changes to reset logic.

The MMCM is now reset using dcm_reset instead of ctrl_reset, this signal is driven high
by the OPB pcore right after reset.

The FIFO is reset when the MMCM is not yet locked or when ctrl_reset is driven high by
the OPB pcore. This is controllable via software.
[adc5g] Expanded the o0_allowed values to include 1.0 for the MMCM.

This was previously set to 2:128 but 1 is actually an allowable value.
Also simplified xps_adc5g.m by using the ismember function instead of
checking if MMCM parameters are within the top/bottom of allowable
values.
[gen_xps_mod_ucf] Added ability to add user-specified constraints to system.ucf

This can be accomplished by setting the USER_UCF_PATH environment variable to a
directory containing files with the .ucf extension. Each of these files is then
appended to the end of system.ucf.
Changed startsg for my toolflow
Merge sma-branch into HEAD (using imerge)

Some changes to adc5g scripts and (apparently) updates to the ROACH2 qdr interface/calibration