nv50/ir: extend moveSources for delta < 0
nvc0/ir: add formatted surface load lib code, move to extra header

OpenGL is nice and makes the user specify a format with an image unit.
OpenCL is evil and doesn't, and what's better than adding a huge load
of functions that we call indirectly to handle the conversion ?
nvc0/ir: implement lowering of surface ops for nve4
nvc0/ir: don't replace load from input in COMPUTE progs with VFETCH
nv50/ir/tgsi: handle TGSI_OPCODE_LOAD,STORE

Squashed and (heavily) modified original patches by Francisco Jerez:
nv50/ir/tgsi: Implement resource LOAD/STORE (wip).
nv50/ir/tgsi: Emit SUST/SULD for surface access, and add CB LOAD/STORE support
nv50/ir/tgsi: Fix/clean up the LOAD/STORE handling code.

Left out for now:
nv50/ir/tgsi: Resource indirect indexing

Treating raw, read-only surfaces as constant buffers (CBs) was removed
because CBs are limited to a size of 64 KiB which isn't desireable, and
because this decision should probably be made by the state tracker.
If we used a number of CB slots for surfaces, it might find that we
cannot accomodate the advertised limit.
nv50/ir/tgsi: add support for atomics
nv50/ir: add support for barriers

nv50 part by Francisco Jerez.
nv50/ir: don't assert on type in Modifier.applyTo if it is 0
nv50/ir/opt: try to make use of SUCLAMP addend
nv50/ir/tgsi: Exclude local declarations from function prototypes.
nv50/ir/ssa: add a few comments regarding RenamePass
nv50/ir: print function inputs and outputs
nv50/ir: fix size adjustment for sched info for multiple functions
nvc0/ir: use large issue delay after RET, too
nvc0/ir: skip back edges when determining latest sched value
nv50/ir: implement splitting of 64 bit ops after RA
nv50/ir: add support for different sampler and resource index on nve4

And remove non-working code for indirect sampler/resource selection.
Will be added back later.

Includes code from "nv50/ir/tgsi: Resource indirect indexing" by
Francisco Jerez (when mixing the R and S handles we can only specify
them via a register, i.e. indirectly, unless we upload all the used
handle combinations to c[] space, which we don't for now).
nv50,nvc0: copy writable flag on surface creation
nouveau: align PIPE_BIND_SHADER,COMPUTE_RESOURCEs to 256 bytes