ARM: sun7i: Enable the I2C controllers

The Allwinner A20 shares the same I2C controller than the one that could
be found on earlier SoCs from Allwinner. There is only a few more of
these controllers. Add all of them in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: Add the pin muxing options for the I2C controllers

The A20 boards we currently have share the same pins for the i2c
controllers they share. Add them to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: cubieboard2: Enable the I2C controllers

The Cubieboard2 uses both the i2c0 and i2c1 controllers. Enable them in
the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: olinuxino-micro: Enable the I2C controllers

The A20-olinuxino-micro uses the first three I2C controllers found on
the A20. Enable them in the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Split out the DT machines for sun6i and sun7i

The A20 and A31 SMP code have a different way of bringing up a new core.
This will prevent us from using the same set of smp_operations for the
two SoCs family.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Simplify restart setup code

Now that we have different machine definitions for different SoCs, we
can remove the DT lookup to get the restart hook we should be using, and
hardcode it in the machine definition instead.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: dts: Add support for the cubieboard3, the CubieTruck

Cubietech introduced a new cubieboard, the CubieTruck. This board added
more output connectors and features 2 GiB of RAM and a Gigabit PHY.

Tested are are uart0 and LEDS which both work as expected.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: Fix the APB2 clock gates register size

The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Add a defconfig for the Allwinner SoCs

So far, the Allwinner SoCs were only supported using the
multi_v7_defconfig. Add a defconfig of our own to have one a bit more
tailor-made.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Order Kconfig options alphabetically

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: Select CLKSRC_MMIO

The Allwinner SoCs timer use the clocksource MMIO functions. We thus
need to select them in Kconfig.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: Report the minimum tick that we can program

We need to wait for at least 2 clock cycles whenever we reprogram our
clockevent timer. Report that the minimum number of ticks we can handle
is 3 ticks, and remove 3 ticks to the interval programmed to reflect
this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: remove IRQF_DISABLED

IRQF_DISABLED is a no-op nowadays, so we can safely remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: change CPU mask to cpu_possible_mask

The interrupt for the timer is a shared interrupt, so any CPU can handle
it. Switch to cpu_possible_mask.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: Increase a bit the clock event and sources rating

We want to keep this driver as the default provider of the clock events
and source, yet some other driver might fit in the "desired" category of
ratings. Hence, we need to increase a bit the rating so that we can have
more flexibility in the ratings we choose.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
clocksource: Add Allwinner SoCs HS timers driver

Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun5i: a10s: Add support for the High Speed Timers

The Allwinner A10s has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun5i: a13: Add support for the High Speed Timers

The Allwinner A13 has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun7i: a20: Add support for the High Speed Timers

The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
reset: Add Allwinner A31 Reset Controller Driver

The Allwinner A31 has an IP maintaining a few other IPs in the SoC in
reset by default. Among these IPs are the High Speed Timers, hence why
we can't use the regular driver construct, and need to call the
registering function directly during machine initialisation.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>