arm: tegra: Board files settings for LP1 0.95V CoreV

Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.

This change is part of the feature to set VCore to 0.95V
Refer to http://git-master/r/124135 for more details
Bug 1035684

Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a)
Reviewed-on: http://git-master/r/124780
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
adapted for use on Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>