ARM: sun7i: Enable the I2C controllers

The Allwinner A20 shares the same I2C controller than the one that could
be found on earlier SoCs from Allwinner. There is only a few more of
these controllers. Add all of them in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: Add the pin muxing options for the I2C controllers

The A20 boards we currently have share the same pins for the i2c
controllers they share. Add them to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: cubieboard2: Enable the I2C controllers

The Cubieboard2 uses both the i2c0 and i2c1 controllers. Enable them in
the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: olinuxino-micro: Enable the I2C controllers

The A20-olinuxino-micro uses the first three I2C controllers found on
the A20. Enable them in the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Initial support for Allwinner's Security ID fuses

Allwinner has electric fuses (efuse) on their line of chips. This driver
reads those fuses, seeds the kernel entropy and exports them as a sysfs
node.

These fuses are most likely to be programmed at the factory, encoding
things like Chip ID, some sort of serial number, etc. and appear to be
reasonably unique.
While in theory, these should be writeable by the user, it will probably
be inconvenient to do so. Allwinner recommends that a certain input pin,
labeled 'efuse_vddq', be connected to GND. To write these fuses however,
a 2.5 V programming voltage needs to be applied to this pin.

Even so, they can still be used to generate a board-unique mac from,
board unique RSA key and seed the kernel RNG.

On sun7i additional storage is available, this is initially used for an
UEFI BOOT key, Secure JTAG key, HDMI-HDCP key and vendor specific keys.

Currently supported are the following known chips:
Allwinner sun4i (A10)
Allwinner sun5i (A10s, A13)
Allwinner sun7i (A20)

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i

This patch shall add support for the sunxi-sid driver to the device
tree for A10, A10s, A13 and A20.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
clk: composite: .determine_rate support

This commit adds .determine_rate support to the composite clock. It will
use the .determine_rate callback from the rate component if available,
and fall back on the mux component otherwise. This allows composite
clocks to enjoy the benefits of automatic clock reparenting.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: factors: fix off-by-one masks

The previous code would generate one bit too long masks, and was
needlessly complicated. This patch replaces it by simpler code that can
generate the masks correctly.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: factors: clear variables before using them

Random bits may get into our factors if we don't clear n, k, m and p.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
clk: sunxi: protect core clocks from accidental shutdown

Some important clocks may get disabled as a side effect of another clock
being disabled, because they have no consumers. This patch implements a
mechanism so those clocks can be claimed by the driver and therefore
remain enabled at all times.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
ARM: sunxi: Split out the DT machines for sun6i and sun7i

The A20 and A31 SMP code have a different way of bringing up a new core.
This will prevent us from using the same set of smp_operations for the
two SoCs family.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Simplify restart setup code

Now that we have different machine definitions for different SoCs, we
can remove the DT lookup to get the restart hook we should be using, and
hardcode it in the machine definition instead.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: Select CLKSRC_MMIO

The Allwinner SoCs timer use the clocksource MMIO functions. We thus
need to select them in Kconfig.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: Add Allwinner SoCs HS timers driver

Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun5i: a10s: Add support for the High Speed Timers

The Allwinner A10s has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun5i: a13: Add support for the High Speed Timers

The Allwinner A13 has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun7i: a20: Add support for the High Speed Timers

The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: Fix the APB2 clock gates register size

The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Order Kconfig options alphabetically

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: register factors clocks behind composite

This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>