cpu: enhance live oc/uc with buildin logic

* Add a basic logic, so the user can't do too much wrong here.
Frequencies have to be descending as well as vsel values. The range is
between 300 mhz and 1500 mhz. Vsel have a range between 15 and 80.

* Also slightly speed up this operation, however the latency here is
still very high.