tcg-ppc64: Implement rotates

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement deposit

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us.  The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Signed-off-by: Richard Henderson <rth@twiddle.net>
disas: Disassemble all ppc insns for the host

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCGType throughout compares

The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly.  Rather than recomputing the TCGType enum from the arch64 bool,
pass around the original TCGType throughout.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Rewrite setcond

Never use MFCR, as the latency is really high.  Even MFOCRF, at half
the latency of MFCR, isn't as fast as we can do with carry tricks.

The ADDIC+SUBFE trick only works for word-sized operands, as we need
carry-out from bit 63.  So for ppc64 we must extend 32-bit inputs.

Use ISEL if available.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement movcond

Signed-off-by: Richard Henderson <rth@twiddle.net>