sbxxx: Add detection for the remaining AMD chipset families.

Also, correct prettyprinting of the registers of the various families,
and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access.

Tested reading/writing on ASRock IMB-A180, and chipset detection on
one of each affected generation by Chris Goodrich from Sage.
sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.

Do not rely on broken firmware to set up the SPI configuration correctly.
Some boards fail with flashrom because the firmware chose too high speeds
for the alternate SPI mode which flashrom uses. Temporarily change the
clock to the lowest common value of 16.5 MHz.

Also, disable fast reads just to be safe.
sbxxx: Cleanup.

 - Move programmer definition to the top.
 - Rewrite array accesses to use indices instead of using pointer arithmetic.
 - Move length check and opcode extraction to a function.
 - Move IMC parameter handling into existing IMC handling function.
 - Split comparing and resetting the FIFO pointer.
sbxxx: Add support for new AMD SPI controller.

This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs
(found in Kabini and Temash).

Tested reading/writing on ASRock IMB-A180.

Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
sbxxx: Add spispeed parameter.

Allow to set the SPI clock frequency on AMD chipsets with a programmer
parameter. If the parameter is given (and matches a possible value), the
SPI clock is set temporarily. Both registers are restored on programmer
shutdown.

Example: ./flashrom -p internal:spispeed="33 MHz" -V

Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz",
"100 MHZ" and "800 kHz" depending on the chipset generation.
debug