Replace 'randomizer' test, which post-processed register traces from the C simulator and verilog model with a cosimulator.
Currently, the cosimulator just parses textual output from the verilog simulator and steps the C simulator appropriately.  It could use VPI, but this is simpler and functionally equivalent.
The advantage of a cosimulator is that it can handle sequencing dependencies between strands in a cycle accurate manner (for example, if one strand writes a location and another reads it).