Phase 3 support for IBM Power ISA 2.07

This patch adds support for the following vector instructions for doing
arithmetic, min, max, shift, pack, unpack and rotate:

  vsubudm, vmaxud, vmaxsd, vminud, vminsd, vmulouw,
  vmuluwm, vmulosw, vmuleuw, vmulesw, vcmpequd, vcmpgtud, vcmpgtsd,
  vrld, vsld, vsrad, vsrd, vpkudus, vpksdus, vpksdss,
  vupkhsw, vupklsw, vmrgew, vmrgow

The following Iops were added to support the above instructions:
  Iop_MullEven32Ux4, Iop_MullEven32Sx4, Iop_Max64Sx2, Iop_Max64Ux2,
  Iop_Min64Sx2, Iop_Min64Ux2, Iop_CmpGT64Ux2, Iop_Rol64x2,
  Iop_QNarrowBin64Sto32Ux4, Iop_QNarrowBin64Uto32Ux4, Iop_NarrowBin64to32x4,

Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>


Bugzilla 324894

git-svn-id: svn://svn.valgrind.org/vex/trunk@2779 8f6e269a-dfd6-0310-a8e1-e2731360e62c