Modify Android mem* routines with CodeAurora versions.

Update the memcpy, memmove, and memset routines to use the
versions from CodeAurora when specified in the bionic/Android.mk
file (actually activated in the BoardConfig.mk file under
device/<vendor>/<board>).  With this change, the mem* routines are
only used for the msm8660, while other platforms will use the
current Android mem* routines.

Future platforms can modify the makefile to use the CodeAurora-based
mem* routines as desired.  This has the benefit of making the CodeAurora-
based routines opt-in instead of opt-out.

Also, PLDSIZE and PLDOFFS can be specified in the BoardConfig.mk as well,
so other platforms with different PLD tunings can use the same code
without modifying the source file itself.

Tests with FileCycler-0.3 showed a slight 1.1% improvement with these
files on an 8660v2, based on the average of three FileCycler runs with
and without the patch.  Since the min/max values did not overlap, and
the average score showed an improvement, we can consider upstreaming these
modifications.

Change-Id: I6946076bc6a88a2a2c8667b09494e1eb31e01ee0
don't hide _nres, necessary for nslookup in busybox.
implement work around for tegra errata 657451

tegra 2 processors have a bug in the register read path of bit 20 of
the CP15 c13, 3 register (used for software thread local storage)

the kernel work-around for this bug is to mux the value from bit 20
into bit 0; since the TLS value used by Android is an aligned address,
bit 0 is known to be available.

Change-Id: If70afa52585d327f9dd5eca479c14ca92532ddd8a
Reviewed-on: http://git-master/r/773
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
TLS: Call kernel helper in additional situations

ARMv6 has HW TLS support, and thus we should be using it rather
than hacking the Linux Kernel to use the software mechanism.
Unfortunately, ARMv6 targets without Thumb2 do not support the
necessary TLS instructions in Thumb Mode. Converting the tls libc
routines to ARM Mode will require an additional branch to switch
modes. Therefore, let's simply use the Kernel's Helper Routine
which already operates in ARM Mode. This changed behavior only
applies if the HAVE_ARM_TLS_REGISTER option is defined.
Otherwise, the existing paradigm is used.

Change-Id: I282697b0ab97cb62affd018494076e6ffa4d392a
msm7627A: Enable 7627A specific memcpy routine

Cache line size for 7627A is 32 bytes. The existing memcpy routine
gives sub-optimal performance for this cache line size. The memcpy
routine has been optimized taking this into consideration. Currently
7627A is the only ARM-v7 target with cache line size of 32 bytes,
hence this optimized code has been featurized under
CORTEX_CACHE_LINE_32 in memcpy.S, memset.S, which can be enabled
by definingTARGET_CORTEX_CACHE_LINE_32 in BoardConfig.mk
This change also adds corresponding cflag definition in Android.mk.

Change-Id: Idea0d1b977f60e0a690ddee36b1d9c67d3c241ef
Use GCC's __attribute__((const)) to reduce code size

__attribute__((const)) is mainly intended for the compiler to optimize
away repeated calls to a function that the compiler knows will return
the same value repeatedly.

By adding __attribute__((const)), the compiler can choose to call the
function just once and cache the return value.  Therefore, this yields
code size reduction.

Here are the reference results by arm-eabi-size for crespo device:

[before]
   text    data     bss     dec     hex filename
 267715   10132   45948  323795   4f0d3

[after]
   text    data     bss     dec     hex filename
 267387   10132   45948  323467   4ef8b

Change-Id: I1d80465c0f88158449702d4dc6398a130eb77195
sha1: code cleanup and use modern C syntax

Apply the following changes:
- Remove out-of-date workaround (SPARC64_GCC_WORKAROUND)
- Use C99 prototype and stdint type

Change-Id: I630cf97f6824f72f4165e0fa9e5bfdad8edabe48
sha1: Use bswap* to optimize byte order

bionic libc already makes use of ARMv6+ rev/rev16 instruction for
endian conversion, and this patch rewrites some parts of SHA1
implementations with swap32 and swap64 routines, which is known to
bring performance improvements.

The reference sha1bench on Nexus S:

[before]
Rounds: 100000, size: 6250K, time: 1.183s, speed: 5.16  MB/s

Change-Id: Id04c0fa1467b3006b5a8736cbdd95855ed7c13e4
[after]
Rounds: 100000, size: 6250K, time: 1.025s, speed: 5.957 MB/sB
dlmalloc: Use ARMv7 version for macro compute_bit2idx and compute_tree_index

The macro compute_bit2idx(X, I) was definied as "I = ffs(X)-1".  This
equals to the operation __builtin_ctz(X), and using the new bit-reversal
instruction would have been better for ARMv7:
    rbit    r0, r0
    clz     r0, r0

This patch re-implements macro compute_bit2idx and compute_tree_index by means
of the above ARMv7 instructions to be more efficient.

Reference: http://hardwarebug.org/2010/01/14/beware-the-builtins/

NOTE: in ICS, the value of macro USE_BUILTIN_FFS was defined to be 0.

Change-Id: I9d9f31d6dab0898e56bb925e29ae1c098d841fe2
linker: optimize SysV ELF hash function

This change can avoid one iterative operation in inner loop.
Inspired by glibc.

Change-Id: I3f641c086654809574289fa6eba0ee1d32e79aa3
Add ARMv7 optimized strlen()

Merge the ARM optimized strlen() routine from Linaro.  Although it is
optimized for ARM Cortex-A9, the performance is still reasonably faster
than the original on Cortex-A8 machines.

Reference benchmark on Nexus S (ARM Cortex-A8; 1 GHz):

[before]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.31712           97        0     1000     1024

[after]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.05855           96        0     1000     1024

Change-Id: I809928804726620f399510af1cd1c852ed754403
linker: Minor optimization of ELF header manipulating

This patch applies the following changes:
 - word alignment to the temporary space for holding ELF header
 - Instead of sequential character comparison of ELF header, use
   pre-calculated value.

Change-Id: I9882e3ffeb25acc05d14803fc7aca3a6a05e3674
Revert "don't hide _nres, necessary for nslookup in busybox."

This reverts commit 0aa56a2ed38e470259b0fcbfc7ba4387149b81db.

Fixed in busybox : http://review.cyanogenmod.com/10762

should be reverted to keep aosp compatibility

Change-Id: I173f0a5cffd8f39ea70bee30a3490e04bbfabf19
Revert "dlmalloc: Use ARMv7 version for macro compute_bit2idx and compute_tree_index"

This reverts commit b3421de186d8b6c7d7a3882ebec695d61e8e7534.

Causing excessive gc calls and instability.
memmove: Fix the abuse of memcpy() for overlapping regions

memcpy is not defined for overlapping regions.

Original author: Chris Dearman <chris@mips.com>

Change-Id: Icc2acc860c932eaf1df488630146f4e07388a444
memcmp: prefetch optimizing for ARM Cortex-A8/A9

The original memcmp() was tweaked for ARM9, which is not optimal for ARM
Cortex-A cores.  This patch merges the prefetch optimizations from
ST-Ericsson and removes NEON slowdowns.

Reference experiement results on Nexus S (ARM Cortex-A8; 1 GHz) using
strbench program:
    http://pasky.or.cz//dev/glibc/strbench/

[before]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.510000 0.000000 2.510000
   8   131072         1.570000 0.010000 1.590000
  32    32768         1.310000 0.000000 1.320000

[after]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.280000 0.000000 2.290000
   8   131072         1.210000 0.000000 1.220000
  32    32768         1.040000 0.000000 1.050000

Change-Id: I961847da96d2025f7049773cd2ddaa08579e78d6
bionic: Update mechanism to detect number of CPU's for msm targets

msm targets use CPU hotplug for power management, which results in
/proc/cpuinfo and /proc/stat to return back incorrect number of
available CPUs for msm configuration.

Use /sys/devices/system/cpu/present instead when indicating total
number of CPUs to userspace processes and let system power
management take care of when to swich CPUs between online/offline
states.

Only 0-N format is supported for detecting number of CPUs.
0-N,M format for detecting number of CPUs is not supported, and is
currently not a valid configuration on msm targets.

ifdef for QCOM_HARDWARE

Change-Id: I40ab2f79ca67cdbf7f1bf87d52007f822ee76269
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/ashmemalloc.cpp.

Change-Id: I7b35bcdaedf3874d17a0e6ce18931c11db1e133d
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/pmemalloc.cpp

Change-Id: Id0732b82ed6c1852def9688544ec92e04afeff00
Add missing define for libcopybit.

This is needed by hardware/qcom/display/libcopybit/copybit.cpp.

Change-Id: Ic50a75b93b39443b772dd4cab67a55f75ad2b5ad