finish encoding all of the interesting details of intrinsics.  Now intrinsics
are only rejected because they can't be encoded into a 32-bit unit, not because
they contain an unencodable feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156978 91177308-0d34-0410-b5e6-96231b3b80d8
Genericize the intrinsics descriptor decoding a bit to make room 
for future expansion, no functionality change yet though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156979 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156985 91177308-0d34-0410-b5e6-96231b3b80d8
Fix compile error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156986 91177308-0d34-0410-b5e6-96231b3b80d8
Remove incorrect pattern for ARM SMML instruction.

Patch by Meador Inge.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156989 91177308-0d34-0410-b5e6-96231b3b80d8
enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits into a
separate side table, using the handy SequenceToOffsetTable class.  This encodes all
these weird things into another 256 bytes, allowing all intrinsics to be encoded this way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156995 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Clean up Hexagon ELF definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156996 91177308-0d34-0410-b5e6-96231b3b80d8
Relax the requirement that the exception object must be an instruction. During
bugpoint-ing, it may turn into something else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156998 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a verifier bug.

Make sure useless (def-only) intervals also get verified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157000 91177308-0d34-0410-b5e6-96231b3b80d8
Never clear <undef> flags on already joined copies.

RegisterCoalescer set <undef> flags on all operands of copy instructions
that are scheduled to be removed. This is so they won't affect
shrinkToUses() by introducing false register reads.

Make sure those <undef> flags are never cleared, or shrinkToUses() could
cause live intervals to end at instructions about to be deleted.

This would be a lot simpler if RegisterCoalescer could just erase joined
copies immediately instead of keeping all the to-be-deleted instructions
around.

This fixes PR12862. Unfortunately, bugpoint can't create a sane test
case for this. Like many other coalescer problems, this failure depends
of a very fragile series of events.

<rdar://problem/11474428>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157001 91177308-0d34-0410-b5e6-96231b3b80d8
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157002 91177308-0d34-0410-b5e6-96231b3b80d8
misched: fix liveness iterators

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157003 91177308-0d34-0410-b5e6-96231b3b80d8
regpressure: Fix getMaxUpwardPressureDelta.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157004 91177308-0d34-0410-b5e6-96231b3b80d8
comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157005 91177308-0d34-0410-b5e6-96231b3b80d8
misched: Added 3-level regpressure back-off.

Introduce the basic strategy for register pressure scheduling.

1) Respect target limits at all times.

2) Indentify critical register classes (pressure sets).
   Track pressure within the scheduled region.
   Avoid increasing scheduled pressure for critical registers.

3) Avoid exceeding the max pressure of the region prior to scheduling.

Added logic for picking between the top and bottom ready Q's based on
regpressure heuristics.

Status: functional but needs to be asjusted to achieve good results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157006 91177308-0d34-0410-b5e6-96231b3b80d8
misched: trace ReadyQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157007 91177308-0d34-0410-b5e6-96231b3b80d8
Remove extraneous ';'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157011 91177308-0d34-0410-b5e6-96231b3b80d8
- Added ExecutionEngine/MCJIT tests
- Added HOST_ARCH to Makefile.config.in
The HOST_ARCH will be used by MCJIT tests filter, because MCJIT supported only x86 and ARM architectures now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157015 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8