sound: soc: codecs: update the TI codec driver for K39

Change-Id: If40c181227981696961d3c563008261e5324e807
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84528
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x: support bt sco playback and recording

support bt sco playback and recording with bt chip as master
and ap-i2s as slave

Change-Id: I0e1bcd6fa71a234a90c830195a7eb2015f71a3b0
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84529
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x: add support for voice call and bt voice call

Change-Id: I773a7c6769ca74d1a02e2d0b8236fdc20af3ecb8
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84530
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x: add dapm route for capture path

Change-Id: I433c35f2ada14f273f85d67f8cf18612bd1e72ea
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84531
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: codecs: aic326x: add mixer controls for configuring CM modes

add mixer controls for configuring CM modes and use the
non-inverting modes for speaker and receiver mixers

Change-Id: I247ccea17d08dc92ac035d6e8070fb146d26b7f5
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84532
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x: turn the mic bias on for headset detction

Change-Id: I3d2bb9de12f72fe7c860bdfe740a2d55676a8aa3
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84533
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: codecs: aic326x: change the init values of aic326x registers

change the init values of aic326x registers to keep unrequired
codec elements powered off to save power, these codec elements would
be turned on when required by dapm

Change-Id: Id843fae2ca1f30b77c402da7ac24e89fb04828b6
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84534
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: codecs: aic326x: enable the headset interrupts after jack registration

Change-Id: I682ccc9ba44f82b8acf836c1703d5d54419da54b
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84535
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x machine: register the sw dev before the card

If sw dev is registered after the card then there would be a kernel
panic if we try to boot the device with Headset connected because
when the card is registered init of every dai link is called from where
we register the jack with codec driver and doing so will enable headset
interrupts which would try to set switch state for an unregistered switch
device

Change-Id: Ie951f41028a3459e4e13d021c80c3f830bbcc533
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84536
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: codecs: aic326x: add process flow for voice call

Change-Id: Ie8ef49b2a76e27e07835fb61bce23ddf69c0b1f9
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84537
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: codecs: aic326x: configure ASI2 as master

configure ASI2 as master and add missing dapm widgets and routes

Change-Id: If2f9c8361888ec40147cd5537f435c91e50cbcc8
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84538
Reviewed-by: Scott Peterson <speterson@nvidia.com>
asoc: tegra: aic326x machine: configure codec as master for voice call

Change-Id: I970ab858399113e4ea0d079779a2cb368af90850
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84539
Reviewed-by: Scott Peterson <speterson@nvidia.com>
serial: tegra: checkpatch cleanups

Fixing build warning.
Cleaning up check patch error and warning.
Re-arranging function to avoid prototype definition of static
functions.

Change-Id: I034f0ca5a1cc2d4c05a79df9df553b87b47d64e2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85092
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
spi: tegra: Add Dma/cpu buffer synchronisation

When dma coherant buffer need to be access by cpu or apb dma,
it is require to calling the dma_sync_single_for_cpu() when cpu
wants to access it and dma_sync_single_for_device() when dma
wants to access the buffer.

Change-Id: I62fc7fced782f3fc2d145c0d5416a4c8cbe30715
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85138
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Revert "mmc: tegra: enabling MMC_PM_KEEP_POWER flag for built_in devices"

This reverts commit caa6566d4fb8539d09276c1bcb818444af675624.

MMC_PM_KEEP_POWER should be used only for sdio as power-on/off code is
implemented only for sdio.

This may also create regression in power.

Bug 938011
Bug 943131

Change-Id: I41a29acb3dd6f3396c97ab78f9704f9b39359675
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/85213
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
video: tegra: dc: in continuous mode mask VBLANK after first frame

A V_BLANK interrupt for each frame does not allow long lp2 idle intervals.
If all windows are clean, mask V_BLANK interrupt after processing it
for updating smart dimmer. It's unmasked again when a new window update
is performed. This will schedule a work for updating smart dimmer for
the new frame.

Bug 920110

Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85137
(cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6)

Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85166
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
ARM: tegra: power: Power off multiple CPUs on-line

Currently on Tegra3 cpu complex is powered off in idle (enters CPU0
LP2 state) only if all secondary CPUs are off-line. This commit adds
an option for CPU0 to enter LP2 while secondary CPUs are still on-line
but have been power gated and entered LP2 state by themselves.

The critical race: secondary CPU is waking up from LP2, while CPU0 is
turning common CPU rail off, is addressed as follows.

1. When entering LP2 state on CPU0:
a) disable GIC distributor
b) check that CPU1-3 are all power-gated (i.e., either off-lined or
have entered LP2)
c) if (b) passes - set all interrupts affinity to CPU0, then
re-enable distributor and continue with CPU complex powering off
d) if (b) fails - re-enable distributor and enter clock-gated (LP3)
state on CPU0
This procedure prevents waking secondary CPUs by GIC SPIs.

2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ
or private timers would happen. This is achieved by disabling timers
and legacy interrupts if CPU1-3 enters LP2 state with external timers
selected as wake sources. Respectively, establish dependency between
turning rail off and LP2 wake timers configuration options.

3. Finally, no IPIs is sent by CPU0 entering LP2.

There are no special changes in wake up procedures - whenever CPU0
is awaken by external interrupt or wake timer, cpu complex is powered
on by h/w, and secondary CPUs that were in LP2 state are ungated by
the same interrupt (off-line CPUs are kept power gated). Hence, there
is no need for CPU1-3 external wake timers to run while the rail is
off, and these timers are stopped. To make sure that none of secondary
CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep
interval of all CPUs.

By default configuration option for powering off multiple on-line CPUs
is disabled on Tegra3.

Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83547
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: cardhu: set dap1 drive strength

Change-Id: I1b3797b021adadd1ad944ede45b5916500a881e6
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84542
Reviewed-by: Scott Peterson <speterson@nvidia.com>
ARM: tegra: Do not unlock CoreSight register access

There is no reason to unlock APB CoreSight register access in the
kernel. The debugger can perform it's own unlock operation as
needed. Keep the registers write-protected to prevent inadvertent
access.

Change-Id: I22f28f76b5dd498b3782ab3380a04f865b59d6fd
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/85039
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
arm: tegra: power: Add AP33 Battery EDP table

Exact copy of AP30 table

Bug 926056

Change-Id: I48730c41605b177d267a569804bbc75a6b94cfba
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/85233
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>