Fixes for capabilities checking w.r.t. Power DFP instructions (VEX
side).  Fixes #297329.  (Maynard Johnson, maynardj@us.ibm.com)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2272 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add %J format to s390_sprintf. New function s390_jump_kind_as_string.
Misc tweaks in the neighbourhood.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2274 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Improve the behaviour of 64-to/from-80 bit QNaN conversions, so that
the QNaN produced is "canonical".  SNaN conversions are unchanged
(because I don't have a definition of what a canonical SNaN is)
although there are some comment updates.  Fixes Mozilla bug #738117.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2276 8f6e269a-dfd6-0310-a8e1-e2731360e62c

POWER Processor decimal floating point instruction support: part 2
(bug #297497) (Carl Love, carll@us.ibm.com) (VEX side)

This commit adds the second set of patches to add decimal floating
point (DFP) support for POWER to Valgrind. Bugzilla 295221 contains
the first set of patches for the adding the POWER support for the DFP
32, 64 and 128-bit sizes. The first set of patches also added support
for the 64 and 128-bit DFP arithmetic instructions and user test code
for the new DFP instructions. The second set of patches, being
submitted in this bugzilla include support for the DFP shift
instructions and format conversion instructions. Specifically, the
list of Power instructions is: dctdp, drsp, dctfix, dcffix, dctqpq,
dctfixq, drdpq, dcffixq, dscri, dscriq, dscli, dscliq.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2277 8f6e269a-dfd6-0310-a8e1-e2731360e62c
ado_treebuild_BB: don't allow loads to be floated past CASs.
(why did this ever work before?)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2278 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Extend CSE to cover CSEing of clean helper calls.  This gives a
significant performance improvement in the baseline simulator (20%) on
some pieces of ARM code.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2280 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Merge branches/TCHAIN from r2271 (its creation point) into trunk.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2296 8f6e269a-dfd6-0310-a8e1-e2731360e62c
We incorrectly stored the archinfo_host argument of iselSB_S390 into
a global variable not realising it points to a stack-allocated variable. 
This caused s390_archinfo_host->hwcaps member to change its value 
randomly over time. It could have caused invalid code to be generated. 
Curious that it did not surface.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2297 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup) Stop x86/amd64 asserting on illegal insns.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2298 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup) remove temp supporting hack "IRStmt_Exit3"


git-svn-id: svn://svn.valgrind.org/vex/trunk@2299 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Ain_XDirect, Ain_XIndir: use short form encodings where possible.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2300 8f6e269a-dfd6-0310-a8e1-e2731360e62c
chainXDirect_ARM: generate direct jumps when possible.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2301 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup): x86: handle a couple more syscall kinds
needed on x86-darwin.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2302 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix debug print for hwcaps adding stfle ad etf2. 
Add VEX_HWCAPS_S390X_STFLE. This should have been part of r2237.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2303 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup): Tighten up some asserts. 


git-svn-id: svn://svn.valgrind.org/vex/trunk@2304 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup): Use ASI and AGSI for increment / decrement if
available.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2305 8f6e269a-dfd6-0310-a8e1-e2731360e62c
(post-tchain-merge cleanup) Stop s390x asserting on illegal insns.
none/tests/s390x/op_exception will now pass.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2306 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Rename to VEX_S390X_MODEL_UNKNOWN.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2307 8f6e269a-dfd6-0310-a8e1-e2731360e62c
tchain optimisation for s390 (VEX bits)
Loading a 64-bit immediate into a register requires 4 insns on a 
z900 machine, the oldest model supported. Depending on hardware
capabilities, newer machines can do the same using 2 insns. 
Naturally, we want to take advantage of that.
However, currently, in disp_cp_chain_me_to_slowEP/fastEP we assume that
the length of loading a 64-bit immediate is a compile time constant:
S390_TCHAIN_LOAD64_LEN 
For what we want to do this constant needs to be a runtime constant.

So in this patch we move this address arithmetic out of the dispatch
code. The general idea being that the value in %r1 does not need to
be adjusted to recover the place to patch. Upon reaching
disp_cp_chain_me_to_slowEP/fastEP %r1 contains the correct address.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2308 8f6e269a-dfd6-0310-a8e1-e2731360e62c
tchain optimization for s390 (continued)
Take advantage of hardware capabilities when loading a 64-bit
immediate. 


git-svn-id: svn://svn.valgrind.org/vex/trunk@2309 8f6e269a-dfd6-0310-a8e1-e2731360e62c