ARM: OMAP3630: add PRM register definitions for ABB

OMAP3630 supports an Adaptive Body-Bias(ABB) LDO as well as some MPU
interrupts related to voltage control that are not present on OMAP34XX.
This patch adds the offsets, register addresses, bitfield shifts and
masks to support this feature.

Change-Id: I0a75ca1171c956bc6c5a689b770bb7d304825427
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: add ABB PRM_IRQSTATUS handlers

Some PRM_IRQSTATUS registers contain a bit to signal that an ABB LDO
transition has completed.  These tranxdone bits exist for every instance
of an ABB LDO; thus these tranxdone bits are supported on 36xx variants
for the MPU voltage domain, and on 44xx variants for the MPU and IVA
voltage domains.

This patch introduces some data structures and helper functions for
checking on and clearing the TRANXDONE bits.  They are a copy-paste of
existing VP functions of similar nature and will be used in forthcoming
patches that control the ABB programming sequence during a DVFS
transition.

Some previous discussion on the design of the ABB PRM handlers can be
found here:
http://article.gmane.org/gmane.linux.ports.arm.omap/63609

Change-Id: I85c8845d8bf717642f8230067db2ff7515a238b5
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: Adaptive Body-Bias structures & data

Starting with OMAP36XX, some voltage domains have an LDO for biasing
voltage to the transistors within that domain.

This LDO has three modes of operation.  The first is Forward Body-Bias
mode (FBB) which boosts performance of transistors at high OPPs by
providng a positive voltage bias.  This comes at a cost of power.

The second mode is Reverse Body-Bias or RBB.  This mode provides a
negative voltage bias which saves on static leakage at lower OPPs.

Finally ABB can also be bypassed (the default state) in which case it
will just follow the voltage of the VP/VC.

This patch introduces the data structures needed to represent the ABB
LDOs in the voltage layer, and populates the appropriate data for 3630
and OMAP4.

Not all voltage domains have an ABB LDO; on OMAP36XX the CORE voltage
domain does not have an ABB ldo, and there are none on OMAP34xx.  In
such cases the voltage data will be marked with OMAP_ABB_NO_LDO.

Change-Id: If51fe172c78b2e20933c80a5f62709bd6fbcfad9
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4, add OMAP5 data, RBB support]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: OPP: add ABB data to voltage tables

The operating mode of the Adaptive Body-Bias ldo is a function of the
voltage at which the VDD is operating and silicon characteristics.

NOMINAL_OPP causes the ABB ldo to be in bypass at that specific voltage.
FAST_OPP causes the ldo to operate in Forward Body-Bias mode.  SLOW_OPP
puts the ldo in Reverse Body-Bias mode.

This patch models this relationship by adding an opp_sel paramter to
struct omap_volt_data and populates this data in the 3630 and 4430
voltage tables.

Not all voltage domains have an ABB ldo and 3430 doesn't have one at
all.  In such cases voltages are marked with OMAP_ABB_NO_LDO.

Change-Id: I503b8b7189b587523eae1f581ed417f53d4cd169
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4, OMAP5 support]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP4460: OPP: Support ABB settings during OPP initialization

Support OMAP4460 ABB detection based on efuse settings
On 4460 all OPPs have pre-determined states for VDD_MPU/IVA's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass, FBB or RBB
depending on a combination of characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Change-Id: Ib46902385f5efcc1826e8112de0ee334c3e3c614
[andrii.tseglytskyi@ti.com, taras@ti.com: squashes and fixes from K3.0]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
ARM: OMAP4470: OPP: Update ABB type according to trim bits

Depending on a trim bits blown into eFuse register CONTROL_STD_FUSE_OPP_DPLL_1
RBB should be enabled at some MPU/IVA OPPs to reduce a leakage on OMAP4470.

 Bit #|       Name      |             Description
------+-----------------+---------------------------------------
  20  | MPU_RBB_TURBO   | 0 - RBB is trimmed and should be used.
  21  | IVA_RBB_TURBO   | 1 - RBB is not trimmed
  22  | MPU_RBB_NITRO   |
  23  | MPU_RBB_NITROSB |
  24  | IVA_RBB_NITRO   |
  25  | IVA_RBB_NITROSB |

Change-Id: Idd76e8dd2f5e55573f6dd6f7515ab57d87b14125
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: Voltage: Add per-voltage domain ABB data

This patch adds struct omap_abb_instance to struct voltagedomain and
populates the data for those voltage domains that have an ABB ldo on
36xx, 44xx, 54xx silicon.

Change-Id: I551c150cb89f12f56e0fe614255c0fa2b1b2f31b
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4, add OMAP5]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: ABB: init & transition functions

The Adaptive Body-Bias LDO can be set to bypass, Forward Body-Bias or
Reverse Body-Bias during a voltage transition.  The ABB programming
sequence depends on whether voltage is scaling up or down.

This patch implements the Adaptive Body-Bias LDO initialization routine
and the transition sequence which is needed after any voltage scaling
operation.

Change-Id: I9c828360433b6f8853c484278b24774bcd4d1857
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[andrii.tseglytskyi@ti.com: rebased to K3.4, RBB support]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: Voltage: call ABB init function

This patch initializes ABB LDO's as a part of the greater voltage domain
initialization sequence.

Change-Id: Ia7e91a8008d429e9257b9d6e6f828eb15092a287
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP3+: DVFS/ABB: make the pre and post scale decision based off Vnom

Currently the ABB LDO prescale and post scale configurations are
done based off voltdm_scale. However when Vsr(SR adjusted voltage)
of the current OPP is the same as Vnom(nominal voltage) of the new
OPP, this results in voltdm_scale not being called.

This has a side-effect of prescale and postscale of ABB not being
invoked either. In case where the new OPP requires FBB, this will
result in device failure.

The right procedure is to move the prescale and postscale notifier
out of the voltage scale API, instead have it on top of dvfs path
and depend on nominal voltage scaling direction to give a proper
trigger on need basis.

NOTE: ABB prescale is skipped in pm.c initial configuration to
take care of various types of bad and correct bootloader
configuration.

Change-Id: Ie953f515ab6182d6fa9be85d0ea83228db63d969
Signed-off-by: Nishanth Menon <nm@ti.com>
[andrii.tseglytskyi@ti.com: Rebased to K3.4]
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Merge branch 'p-linux-omap-3.4' into p-android-omap-3.4

* p-linux-omap-3.4:
  ARM: OMAP3+: DVFS/ABB: make the pre and post scale decision based off Vnom
  ARM: OMAP3+: Voltage: call ABB init function
  ARM: OMAP3+: ABB: init & transition functions
  ARM: OMAP3+: Voltage: Add per-voltage domain ABB data
  ARM: OMAP4470: OPP: Update ABB type according to trim bits
  ARM: OMAP4460: OPP: Support ABB settings during OPP initialization
  ARM: OMAP3+: OPP: add ABB data to voltage tables
  ARM: OMAP3+: Adaptive Body-Bias structures & data
  ARM: OMAP3+: add ABB PRM_IRQSTATUS handlers
  ARM: OMAP3630: add PRM register definitions for ABB

Change-Id: Ia9be320b6c94bc545bcaffe632afd9061c2d90ac
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
ARM: OMAP5: Use arm revision for CPU identification for incorrect efused ES2.0 samples

The OMAP silicon revision is not efused correctly for OMAP5 ES2.0 silicon.
So use arm revision for now to identify the SOC version.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
--
[only append change-id and port to p-linux-omap-3.4]]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: I63b669b71a4f3aa72761a24cb2bbad8fbbcb2c75
ARM: OMAP54XX: hwmod data: use correct clock name for MMC1

Change-Id: Ib35634539ec4f0fc711b2a7c3099f32a0d8b59f6
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Viswanath Puttagunta <vishp@ti.com>
ARM: OMAP5430: hwmod data: Fix break caused by "Clean context_offs/clkctrl_offs usage"

<re-applying> since initial ES2.0 data patch reverted the change:
commit: a720ac8d6c7415d89527b2d9020f7775d0d7d8be
--
original patch description:

patch: ARM: OMAP5430: hwmod data: Clean context_offs/clkctrl_offs usage
commit: 498c4e3bbf687a15d22deec27689734f4b43fe96

causes omap5 platform boot failure.

Reason:
removing "clkctrl_offs =  OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET"
causes dss_dispc,dss_dsi1_a,dss_dsi1_c,dss_hdmi,dss_rfbi as in-accessible

If clkctrl_offs was present, _wait_target_ready will timeout and
hence causing subsequent functions not to execute and hence the
print

"omap_hwmod: dss_dispc: cannot be enabled (3)"
--

whereas if clkctrl_offs is removed, _wait_target_ready will return
without checking the target and hence system crashes due to
"update_syscache" execution

Change-Id: I51dcb73dd50181e07ec0f9d56060542fe856ec94
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP54XX: clock data: add alias for dmic_gfclk

Patch adds alias dmic_fck -> dmic_gfclk, which is needed for
omap dmic driver.

Change-Id: I4a8a9094dbdea0c7ce1b662ee0f26b47a718d6bb
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
ARM: OMAP54XX: voltagedomains: fix initialization for OMAP5430_REV_ES2_0

Patch adds proper initialization in for OMAP5430_REV_ES2_0,
before only OMAP5432_REV_ES2_0 was properly initialized.

Change-Id: Idda959dec85e90437bb453b821155fa88155ba27
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP54XX: mux: correct names for mcpdm

Names for mcpdm should be properly updated to be aligned
with mux data.

Change-Id: I6aa0ca0caac439ee41f3c30fa20691fc871b72ed
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
ARM: OMAP4: Tablet/SDP: Enable SmartReflex on init

Enable SmartReflex on init on SDP4430 and Tablet44xx boards.

Change-Id: I4dfb2f83399d18b9b965cf0ab319c90666ad8cfd
Signed-off-by: Taras Kondratiuk <taras@ti.com>
ARM: OMAP4: board: Configure UART autosuspend delay

Set UART autosuspend delay to 3000ms by default.
This allows CORE to reach retention during CPUidle.
3 sec value was used in k3.0 so it is acceptable.

Change-Id: I887a78490a9367d7b64f485e037ba852ac56de57
Signed-off-by: Taras Kondratiuk <taras@ti.com>
ARM: OMAP4: PM: Enable Voltage Transition in LP states

Now the Voltage Transition in LP states is disabled because
omap5_has_auto_ret() feature check always returns false for OMAP4.
But OMAP4 supports Voltage Transition in LP states and Retention voltage
reliably by default.
Hence, enable Enable Voltage Transition in LP states for OMAP4 SoCs and
disable it for OMAP5 only.

Change-Id: Ie4a8af9abeb8c84aa823cd9388af88e91f35d78b
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>