[DRIVERS] pl011: Added initialization for interrupt FIFO level select register.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] pl011: Made pl011_getc_sleepable() more robust and compliant with real-hardware.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Updated host irq subsystem to count irqs.

Signed-off-by: Anup Patel <anup@brainfault.org>
[COMMANDS] Consolidated vapool and ram commands into a common host command.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Minor cleanups in host irq subystem.

Signed-off-by: Anup Patel <anup@brainfault.org>
[COMMANDS] Added irq sub-command under host command to display host irq statistics.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Added CPU and Instruction Set specific CFLAGS.

Signed-off-by: Anup Patel <anup@brainfault.org>
[TESTS] Cleanup TCL test suite for Basic Test on Realview-PB-A8 guest.

Signed-off-by: Anup Patel <anup@brainfault.org>
CPU Host Address Space Initialization

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[CORE] Updated stdio to have one input and one output device instead of just one device for both input and output.

This patch make stdio more generic. This will be useful in desktops where input device (usually keyboard) and output device (text mode video device) are different.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Added initial compilable code for cortex-a15 with virtualization extension.

This patch adds arm32ve cpu directory for cortex-a15 with virtualization support (i.e. cortex-a15-ve).
For now arm32ve directory is almost same as arm32 directory.
We progessively strip down arm32ve and change it gradually utilize ARM virtualization extensions.

Folks interested in ARM virtualization extensions should review and watch changes in arm32ve.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Added code to enter hypervisor mode at startup time in arm32ve.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Moved CPSR_MODE_HYPERVISOR define from arm32 to arm32ve

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge pull request #5 from hschauhan/master

x86 CPU Host Address Space Initialization
[ARM] Added stub for setting up translation table in C code.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] For arm32ve physical_addr_t and physical_size_t types are 64-bit due to use of LPAE.

This patch changes physica_addr_t and physical_size_t for cortex-a15-ve support.
It also fixed related compiler warnings.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Splitted reserved space expected by host aspace from arch code into core reserved space and arch reserved space.

This patch splits reserved space into core reserved space (for VAPOOL bitmap and RAM bitmap in core code) and arch reserved space (optional space for keeping architecture specific reserved memory e.g. pool of page tables).

This patch adds to the meaning of reserved space in vmm_host_aspace_init() and make it more flexible. Previously it was mandatory to keep architecture specific reserved memory appended to reserved space expected by vmm_host_aspace_init(). With this patch in-place we dont have this restriction any more. The architecture specific code can keep its reseved memory any where provided it does not overlap code space and core reserved space.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Removed unwanted code from arm32ve.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Add ARM V5 (ARM9) support to xvisor.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] separate ARMV5 and ARMV7 atomic operations.

Signed-off-by: Anup Patel <anup@brainfault.org>