lm32: add tlb control registers

Add TLBVADDR, TLBPADDR and TLBBADVADDR registers. These are used to
control the data and instruction TLBs.

Control functions like flushing and invalidating an entry are executed by
writing to the TLBVADDR register. An entry can be updated by writing to the
TLBPADDR (before writing the virtual frame number to TLBVADDR, with the
lower bits zero to indicate a NOOP).

The lowest bit in the TLBVADDR and TLBPADDR register is used to address the
corresponding TLB.

After a TLB exception has happened, the TLBVADDR register is automatically
preloaded with the missed virtual frame number. Because of this, an
exception handler can read the missed virtual address by reading
TLBBADVADDR register and set the physical frame number by writing the
TLBPADDR register.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
lm32: add PSW register

Add the processor status word register. This register is used to enable the
TLBs and the (non-privileged) user mode. If an exception occurs, the these
enable bits will be saved and cleared. After an eret or bret opcode is
executed, these bits will be restored.

For backward compatibility, the lower three bits of this register are
shadowed from the original IE register. A new program can then only use
this register, eg. saving the state on an ISR, while older programs can
still use the IE register.

Signed-off-by: Michael Walle <michael@walle.cc>
lm32: add MMU flag to CFG2 register

Use the most significant bit because Lattice will likely add new feature at
the lower bits.

Signed-off-by: Michael Walle <michael@walle.cc>
lm32: make wcsr, bret and eret privileged

Make wcsr, bret and eret NOOPs if the processor is not in kernel mode.

Signed-off-by: Michael Walle <michael@walle.cc>
lm32: initial ITLB implemenation

This patch adds the instruction translation lookaside buffer.

Miss exceptions are delayed until the X stage and if the instruction is
still qualified (eg. not killed and still valid) the exception is taken.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
lm32: initial DTLB implemenation

This patch add the data translation lookaside buffer.

The pipeline is stalled for one cycle every load and store instruction
if the DTLB is enabled. This cycle is needed for the TLB llokup. The
lookup result is needed in the X stage to correctly handle a potential
exception.

Additionally, there are read only and cache inhibit flags in a TLB
entry.  Writes to a read-only page will raise a DTLB fault exception. If
the cache inhibit flag is set, load and stores will skip the data cache
and go directly to the wishbone bus instead.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Yann Sionneau <yann.sionneau@gmail.com>
lm32: privilege exception support

Raise a privilege exception if we are in user mode and one of the following
opcodes are executed: wcsr, eret, bret.

Signed-off-by: Michael Walle <michael@walle.cc>
lm32: import qemu test cases

Import the TCG test cases from QEMU. Emulate the lm32_sys device in the
lm32 test bench. From time to time these test cases will be synchronized
with QEMU.

Signed-off-by: Michael Walle <michael@walle.cc>