[from now] Thu Dec 13 16:38:22 JST 2012

diff --git a/2nd/sdcard/sd_cache.v b/2nd/sdcard/sd_cache.v
index c341c29..9808536 100644
--- a/2nd/sdcard/sd_cache.v
+++ b/2nd/sdcard/sd_cache.v
@@ -1,34 +1,9 @@
 module sd_cache(input clk,

-                output       sd_clk,
-                output       sd_ce,
-                output       sd_out,
-                input        sd_in,
-
-                output [7:0] sd_data,
                 input [31:0] sd_addr,
-                input        sd_go,
-                output       sd_ready);
-
-   wire [8:0] sd_index;
-   reg sd_controller_go;
-   wire sd_busy;
-
-   reg [22:0] current_block;
-   wire [22:0] required_block;
-
-   sd_cont sd_cont_inst
-      (.clk(clk),
-       .sd_clk(sd_clk),
-       .sd_ce(sd_ce),
-       .sd_out(sd_out),
-       .sd_in(sd_in),
-
-       .sd_data(sd_data),
-       .sd_addr(required_block),
-       .sd_index(sd_index),
-       .sd_go(sd_controller_go),
-       .sd_busy(sd_busy));
+                output       to_load,
+                input        sd_busy
+                output       ready);

    assign required_block =  sd_addr[31:9];
    assign sd_index = sd_addr[8:0];
[from now] Thu Dec 13 16:38:40 JST 2012

diff --git a/2nd/sdcard/sdcard.v b/2nd/sdcard/sdcard.v
new file mode 100644
index 0000000..fda8918
--- /dev/null
+++ b/2nd/sdcard/sdcard.v
@@ -0,0 +1,41 @@
+module sd_cache(input clk,
+
+                output       sd_clk,
+                output       sd_ce,
+                output       sd_out,
+                input        sd_in,
+
+                output [7:0] sd_data,
+                input [31:0] sd_addr,
+                input        sd_go,
+                output       sd_ready);
+
+   wire [22:0] required_block;
+   wire sd_busy;
+   wire sd_controller_go;
+
+   wire [8:0] sd_index;
+
+   assign sd_index = sd_addr[8:0];
+
+   sd_cont sd_cont_inst
+      (.clk(clk),
+       .sd_clk(sd_clk),
+       .sd_ce(sd_ce),
+       .sd_out(sd_out),
+       .sd_in(sd_in),
+
+       .sd_data(sd_data),
+       .sd_addr(sd_addr[31:9]),
+       .sd_index(sd_index),
+       .sd_go(sd_controller_go),
+       .sd_busy(sd_busy));
+
+   sd_cache sd_cache_inst
+      (.clk(clk),
+       .sd_addr(sd_addr),
+       .to_load(sd_controller_go),
+       .sd_busy(sd_busy),
+       .ready(sd_ready))
+
+endmodule
diff --git a/2nd/sdcard/test_sd_cache.v b/2nd/sdcard/test_sd_cache.v
new file mode 100644
index 0000000..de3dd46
--- /dev/null
+++ b/2nd/sdcard/test_sd_cache.v
@@ -0,0 +1,58 @@
+module test_sd ();
+
+   reg clk;
+   reg reset;
+
+   reg [31:0] inst, rs;
+   reg branch_taken;
+   wire [31:0] pc;
+
+   program_counter dut (clk, reset, inst, rs, branch_taken, pc);
+
+   task pc_is;
+      input [31:0] expected;
+      begin
+         if (pc !== expected) begin
+            $display ("FAIL %d != %d", pc, expected);
+            $stop;
+         end
+      end
+   endtask
+
+   initial begin
+      reset <= 1;
+      #22;
+      reset <= 0;
+      #10;
+
+      rs <= 0;
+      branch_taken <= 0;
+
+      inst <= 32'b11100000000000000000000000110101;
+      #10 pc_is(53);
+
+      inst <= 32'b11100100010000000000000000000000;
+      #10 rs <= 5; inst <= 32'h00000000;
+      #10 pc_is(5);
+
+      inst <= 32'b11101000000000000000000000110101;
+      #10 pc_is(53);
+      inst <= 32'b11110000000000000000000000000000;
+      #10 pc_is(5);
+
+      inst <= 32'b10000000000000000000000000110101;
+      #10 inst <= 32'h00000000;
+      #10 branch_taken <= 1;
+      #10 pc_is(58);
+
+   end
+
+   // geenrate clock to sequence tests
+   always begin
+      clk <= 1;
+      #5;
+      clk <= 0;
+      #5;
+   end
+
+endmodule
[from now] Thu Dec 13 16:49:59 JST 2012

diff --git a/2nd/sdcard/sd_cache.v b/2nd/sdcard/sd_cache.v
index 9808536..65fc87d 100644
--- a/2nd/sdcard/sd_cache.v
+++ b/2nd/sdcard/sd_cache.v
@@ -1,8 +1,8 @@
 module sd_cache(input clk,

                 input [31:0] sd_addr,
+                input        sd_busy,
                 output       to_load,
-                input        sd_busy
                 output       ready);

    assign required_block =  sd_addr[31:9];
diff --git a/2nd/sdcard/test_sd_cache.v b/2nd/sdcard/test_sd_cache.v
index de3dd46..5028e84 100644
--- a/2nd/sdcard/test_sd_cache.v
+++ b/2nd/sdcard/test_sd_cache.v
@@ -1,50 +1,60 @@
-module test_sd ();
+module test_sd_cache ();

    reg clk;
-   reg reset;

-   reg [31:0] inst, rs;
-   reg branch_taken;
-   wire [31:0] pc;
+   reg [31:0] sd_addr;
+   reg sd_busy;

-   program_counter dut (clk, reset, inst, rs, branch_taken, pc);
+   wire to_load, ready;

-   task pc_is;
-      input [31:0] expected;
+   sd_cache dut (clk, sd_addr, sd_busy, to_load, ready);
+
+   task assert_load;
       begin
-         if (pc !== expected) begin
-            $display ("FAIL %d != %d", pc, expected);
+         if (to_load !== 1'b1) begin
+            $display ("FAIL: not loaded");
             $stop;
          end
       end
    endtask

-   initial begin
-      reset <= 1;
-      #22;
-      reset <= 0;
-      #10;
-
-      rs <= 0;
-      branch_taken <= 0;
+   task assert_ready;
+      begin
+         if (ready !== 1'b1) begin
+            $display ("FAIL: not ready");
+            $stop;
+         end
+      end
+   endtask

-      inst <= 32'b11100000000000000000000000110101;
-      #10 pc_is(53);
+   initial begin
+      #28;

-      inst <= 32'b11100100010000000000000000000000;
-      #10 rs <= 5; inst <= 32'h00000000;
-      #10 pc_is(5);
+      sd_addr <= 32'b00000000;
+      #10;
+      assert_load();
+      sd_busy <= 1'b1;
+      #50;
+      sd_busy <= 1'b0;
+      #10;
+      assert_ready();

-      inst <= 32'b11101000000000000000000000110101;
-      #10 pc_is(53);
-      inst <= 32'b11110000000000000000000000000000;
-      #10 pc_is(5);
+      sd_addr <= 32'b00000055;
+      #10;
+      assert_ready();

-      inst <= 32'b10000000000000000000000000110101;
-      #10 inst <= 32'h00000000;
-      #10 branch_taken <= 1;
-      #10 pc_is(58);
+      sd_addr <= 32'b00030005;
+      #10;
+      assert_load();
+      sd_busy <= 1'b1;
+      #50;
+      sd_busy <= 1'b0;
+      #10;
+      assert_ready();

+      sd_addr <= 32'b00030005;
+      #10;
+      assert_ready();
    end

    // geenrate clock to sequence tests
[from now] Thu Dec 13 17:07:00 JST 2012

diff --git a/2nd/sdcard/sd_cache.v b/2nd/sdcard/sd_cache.v
index 65fc87d..101ab43 100644
--- a/2nd/sdcard/sd_cache.v
+++ b/2nd/sdcard/sd_cache.v
@@ -2,52 +2,40 @@ module sd_cache(input clk,

                 input [31:0] sd_addr,
                 input        sd_busy,
-                output       to_load,
-                output       ready);
+                output reg   to_load,
+                output reg   ready);
+
+   reg [22:0] current_block, loading_block;
+   reg prev_busy;

    assign required_block =  sd_addr[31:9];
    assign sd_index = sd_addr[8:0];

-   reg [2:0] state;
-   // 000: default
-   // 001: loaded (ready)
-   // 010: required, loading started (go = 1, busy = 1)
-   // 011: required, load finished (busy = 0)
-
-   initial
-     state <= 3'b0;
+   initial begin
+      current_block <= 22'b1111111111111111111111;
+      loading_block <= 22'b1111111111111111111111;
+      prev_busy <= 1'b0;
+      ready <= 1'b0;
+   end

    always @ (posedge(clk)) begin
-      sd_controller_go <= 1'b0;
-      case (state)
-        3'b000:
-           if (sd_go == 1'b1)
-             if (current_block == required_block)
-               state <= 3'b001;
-             else begin
-                state <= 3'b100;
-                sd_controller_go <= 1'b1;
-             end
-           else
-              state <= state;
-
-        3'b001:
-          state <= 3'b010;
-
-        3'b010:
-          state <= 3'b000;
-
-        3'b100:
-          if (sd_controller_go == 1'b0 && sd_busy == 1'b0)
-            state <= 3'b101;
-
-        3'b101: begin
-           state <= 3'b0;
-           current_block <= required_block;
-        end
-      endcase
+      prev_busy <= sd_busy;
+      to_load   <= 1'b0;
+      ready     <= 1'b0;
+
+      if (required_block == current_block) begin
+         ready <= 1'b1;
+         to_load <= 1'b0;
+      end else if (sd_busy == 1'b0) begin
+         if (prev_busy == 1'b1) begin
+            current_block <= loading_block;
+            if (loading_block == required_block)
+              ready <= 1'b1;
+         end else begin
+            loading_block <= required_block;
+            to_load <= 1'b1;
+         end
+      end
    end

-   assign sd_ready = state == 3'b010 ? 1'b1 : 1'b0;
-
 endmodule
diff --git a/2nd/sdcard/test_sd_cache.v b/2nd/sdcard/test_sd_cache.v
index 5028e84..f63c952 100644
--- a/2nd/sdcard/test_sd_cache.v
+++ b/2nd/sdcard/test_sd_cache.v
@@ -28,31 +28,34 @@ module test_sd_cache ();
    endtask

    initial begin
+      sd_busy <= 1'h1;
       #28;
+      sd_busy <= 1'h0;
+      #10;

-      sd_addr <= 32'b00000000;
+      sd_addr <= 32'h00000000;
       #10;
       assert_load();
-      sd_busy <= 1'b1;
+      sd_busy <= 1'h1;
       #50;
-      sd_busy <= 1'b0;
+      sd_busy <= 1'h0;
       #10;
       assert_ready();

-      sd_addr <= 32'b00000055;
+      sd_addr <= 32'h00000055;
       #10;
       assert_ready();

-      sd_addr <= 32'b00030005;
+      sd_addr <= 32'h00030005;
       #10;
       assert_load();
-      sd_busy <= 1'b1;
+      sd_busy <= 1'h1;
       #50;
-      sd_busy <= 1'b0;
+      sd_busy <= 1'h0;
       #10;
       assert_ready();

-      sd_addr <= 32'b00030005;
+      sd_addr <= 32'h00030005;
       #10;
       assert_ready();
    end
[from now] Thu Dec 13 17:33:37 JST 2012

diff --git a/2nd/sdcard/sd_cache.v b/2nd/sdcard/sd_cache.v
index 101ab43..ebdfbc9 100644
--- a/2nd/sdcard/sd_cache.v
+++ b/2nd/sdcard/sd_cache.v
@@ -1,15 +1,16 @@
 module sd_cache(input clk,

+                input        sd_go,
                 input [31:0] sd_addr,
                 input        sd_busy,
                 output reg   to_load,
                 output reg   ready);

    reg [22:0] current_block, loading_block;
+   wire [22:0] required_block;
    reg prev_busy;

    assign required_block =  sd_addr[31:9];
-   assign sd_index = sd_addr[8:0];

    initial begin
       current_block <= 22'b1111111111111111111111;
@@ -23,17 +24,17 @@ module sd_cache(input clk,
       to_load   <= 1'b0;
       ready     <= 1'b0;

-      if (required_block == current_block) begin
-         ready <= 1'b1;
-         to_load <= 1'b0;
-      end else if (sd_busy == 1'b0) begin
-         if (prev_busy == 1'b1) begin
-            current_block <= loading_block;
-            if (loading_block == required_block)
-              ready <= 1'b1;
-         end else begin
-            loading_block <= required_block;
-            to_load <= 1'b1;
+      if (sd_go == 1'b1) begin
+         if (required_block == current_block) begin
+            ready <= 1'b1;
+            to_load <= 1'b0;
+         end else if (sd_busy == 1'b0) begin
+            if (prev_busy == 1'b1) begin
+               current_block <= loading_block;
+            end else begin
+               loading_block <= required_block;
+               to_load <= 1'b1;
+            end
          end
       end
    end
diff --git a/2nd/sdcard/sdcard.v b/2nd/sdcard/sdcard.v
index fda8918..49f10a7 100644
--- a/2nd/sdcard/sdcard.v
+++ b/2nd/sdcard/sdcard.v
@@ -1,4 +1,4 @@
-module sd_cache(input clk,
+module sdcard(input clk,

                 output       sd_clk,
                 output       sd_ce,
@@ -33,9 +33,10 @@ module sd_cache(input clk,

    sd_cache sd_cache_inst
       (.clk(clk),
+       .sd_go(sd_go),
        .sd_addr(sd_addr),
        .to_load(sd_controller_go),
        .sd_busy(sd_busy),
-       .ready(sd_ready))
+       .ready(sd_ready));

 endmodule
diff --git a/2nd/sdcard/test_sd_cache.v b/2nd/sdcard/test_sd_cache.v
index f63c952..57c5ce4 100644
--- a/2nd/sdcard/test_sd_cache.v
+++ b/2nd/sdcard/test_sd_cache.v
@@ -3,16 +3,17 @@ module test_sd_cache ();
    reg clk;

    reg [31:0] sd_addr;
+   reg sd_go;
    reg sd_busy;

    wire to_load, ready;

-   sd_cache dut (clk, sd_addr, sd_busy, to_load, ready);
+   sd_cache dut (clk, sd_go, sd_addr, sd_busy, to_load, ready);

    task assert_load;
       begin
          if (to_load !== 1'b1) begin
-            $display ("FAIL: not loaded");
+            $display ("FAIL: load");
             $stop;
          end
       end
@@ -21,6 +22,24 @@ module test_sd_cache ();
    task assert_ready;
       begin
          if (ready !== 1'b1) begin
+            $display ("FAIL: ready");
+            $stop;
+         end
+      end
+   endtask
+
+   task assert_not_load;
+      begin
+         if (to_load !== 1'b0) begin
+            $display ("FAIL: not load");
+            $stop;
+         end
+      end
+   endtask
+
+   task assert_not_ready;
+      begin
+         if (ready !== 1'b0) begin
             $display ("FAIL: not ready");
             $stop;
          end
@@ -32,14 +51,18 @@ module test_sd_cache ();
       #28;
       sd_busy <= 1'h0;
       #10;
+      sd_go <= 1'b0;

+      sd_go <= 1'b1;
       sd_addr <= 32'h00000000;
       #10;
       assert_load();
+      assert_not_ready();
       sd_busy <= 1'h1;
       #50;
       sd_busy <= 1'h0;
       #10;
+      #10;
       assert_ready();

       sd_addr <= 32'h00000055;
@@ -49,15 +72,23 @@ module test_sd_cache ();
       sd_addr <= 32'h00030005;
       #10;
       assert_load();
+      assert_not_ready();
       sd_busy <= 1'h1;
       #50;
       sd_busy <= 1'h0;
       #10;
+      #10;
       assert_ready();

       sd_addr <= 32'h00030005;
       #10;
       assert_ready();
+
+      sd_go <= 1'b0;
+      sd_addr <= 32'h00020005;
+      #10;
+      assert_not_load();
+      assert_not_ready();
    end

    // geenrate clock to sequence tests
diff --git a/2nd/top.vhd b/2nd/top.vhd
index af0fd7f..74cd897 100644
--- a/2nd/top.vhd
+++ b/2nd/top.vhd
@@ -149,7 +149,7 @@ architecture top of top is
 			keycode    : out std_logic_vector(7 downto 0));
 	end component;

-	component sd_cache is
+	component sdcard is
 		port (
 			clk : in STD_LOGIC;
 			sd_clk : out STD_LOGIC;
@@ -276,7 +276,7 @@ begin  -- test
 		 key_status => key_status,
 		 keycode    => keycode);

-	sd_inst : sd_cache port map
+	sd_inst : sdcard port map
 		(clk      => iclk,

 		 sd_clk   => SD_SCLK,
diff --git a/compiler_set/simulator/simulator.cpp b/compiler_set/simulator/simulator.cpp
index f17acab..94025ba 100644
--- a/compiler_set/simulator/simulator.cpp
+++ b/compiler_set/simulator/simulator.cpp
@@ -605,7 +605,7 @@ int simulate(simulation_options * opt)
 					ROM[IRS] = b;
 					break;
 				}
-			case READSD:
+		case READSD:
 				IRT = sd_card.read_at(IRS);
 				logger.reg("READSD", get_rt(inst), IRT);
 				break;
[from now] Thu Dec 13 17:44:34 JST 2012

diff --git a/2nd/sdcard/sdcard.v b/2nd/sdcard/sdcard.v
index 49f10a7..79722e8 100644
--- a/2nd/sdcard/sdcard.v
+++ b/2nd/sdcard/sdcard.v
@@ -10,7 +10,6 @@ module sdcard(input clk,
                 input        sd_go,
                 output       sd_ready);

-   wire [22:0] required_block;
    wire sd_busy;
    wire sd_controller_go;