i965/gen6+: Adjust stencil buffer size after computing miptree layout.

Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer.  Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size.  This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.

(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)

For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196).  Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture.  However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.

This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.

NOTE: This is a candidate for the 8.0 release branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit bde833c9d014ad8aebfab0d2285184d7e6d5896d)
i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.

Also add a clarifying comment for why the width/height doesn't need
adjustment for Gen7.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 32c7b2769cbe80ff56d1c73c4f9b62f13f577c8d)
i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.

This makes it more convenient for blorp functions to get access to
Intel-specific data inside the renderbuffer objects.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit e14b1288ef5b5b6091facaecd42e86f0a8157f28)
i965/blorp: store surface width/height in brw_blorp_mip_info.

Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (it's necessary when a W-tiled surface
is being mapped as Y-tiled).  With this patch, we look up the width
and height when setting up the blit, and store them in
brw_blorp_mip_info.  This allows us to do the necessary tweak in the
brw_blorp_blit_params constructor (where it makes more sense).  It
also reduces the need to keep track of level and layer in
brw_blorp_mip_info, so that a future patch can eliminate them
entirely.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 09b0fa8499d8035fa31ccb2b550056305fbd149b)
i965/blorp: store x and y offsets in brw_blorp_mip_info.

Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required).  This is a bug, since the user might try to blit
to and from levels/layers other than 0.

To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).

So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.

As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d)
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().

Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination.  As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.

This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.

Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 3123f0621561549c4566248100661ef77cab2834)
i965/blorp: Account for offsets when emitting SURFACE_STATE.

Fixes piglit tests "framebuffer-blit-levels {read,draw} depth".

Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit f04f219906e40a6647a10fd9c1928509fe25fb84)
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.

When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.

Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.

This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.

Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
i965/blorp: don't reduce stencil alignment restrictions when multisampling.

When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.

Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels.  However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.

Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits.  The overly conservative alignment restrictions will be
removed in the patch that follows.  Doing this fix now will prevent
the subsequent patch from introducing regressions.

Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 1a75063d5f829547b75b60ae64bddf3905b4cb8f)
i965/blorp: Reduce alignment restrictions for stencil blits.

Previously, we aligned all stencil blit operations to multiples of the
size of a tile, since stencil buffers use W-tiling, and blorp has to
approximate this by configuring the 3D pipeline for Y-tiling and
swizzling coordinates.

However, this was unnecessarily conservative; it turns out that the
differences between W-tiling and Y-tiling are confined to 32-byte
sub-tiles within the 4k tiling pattern; the layout of these 32-byte
sub-tiles within the larger 4k tile is the same (8 sub-tiles across by
16 sub-tiles down, in column-major order).  Therefore we only need to
align stencil blit operations to multiples of the sub-tile size.

Note: although the performance improvement of this change is probably
quite small, the fact that W-tiling and Y-tiling formats only differ
within 32-byte sub-tiles will be essential in a future patch to ensure
that stencil blits work correctly between parts of the miptree other
than level/layer 0.  Making this change provides handy documentation
(and validation) of this fact.

Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 5fd67fac14d7f35c311eb5c671be8d4ae9b2ea37)
i965/blorp: Fix offsets and width/height for stencil blits.

Fixes piglit test "framebuffer-blit-levels draw stencil".

Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 1a5d4f7cb2367c7863b28efbd78e9169114baf42)
i965/blorp: Increase Y alignment for multisampled stencil blits.

This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp:
Reduce alignment restrictions for stencil blits), which causes
multisampled stencil blits to work incorrectly on Sandy Bridge.

When blitting to or from a normal stencil buffer, we have to use a
coordinate transformation that swizzles coordinates to account for the
fact that stencil buffers use W tiling, but the most similar tiling
format available for textures and render targets is Y tiling.  The
differences between W and Y tiling cause pixels to be scrambled within
a block of size 8x4 (width x height) as measured relative to a W tile,
or 16x2 as measured relative to a Y tile.  So in order to make sure
that pixels at the edges of the blit aren't lost, we need to align the
rendering rectangle (and the buffer sizes) to multiples of the 8x4
block size.  This alignment happens in the brw_blorp_blit_params
constructor, whereas the determination of how to swizzle the
coordinates happens during code generation, in the
brw_blorp_blit_program class.

When blitting to or from a multisampled stencil buffer, the coordinate
swizzling is more complex, because it has to account for the
interleaving pattern of samples, which uses 4x4 blocks for 4x MSAA and
8x4 blocks for 8x MSAA.  The end result is that if multisampling is in
use, the 16x2 block size (relative so a Y tile) needs to be expanded
to 16x4, and the corresponding size relative to a W tile expands to
8x8.

The problem doesn't affect Ivy Bridge severely enough to crop up in
Piglit tests because on Ivy Bridge we have to disable multisampling
when blitting *to* a multisampled stencil buffer (the blorp compiler
generates code to compensate for the fact that multisampling is
disabled).  However I suspect a bug is still present because we don't
disable multisampling when blitting *from* a multisampled stencil
buffer.

This patch fixes the problem by doubling the vertical alignment
requirement when blitting to or from a multisampled stencil buffer,
and multisampling has not been disabled.

In the long run I would like to rework the brw_blorp_blit_params
constructor--it's difficult to follow and has had several subtle bugs
like this one.  However this band-aid fix should be suitable for
cherry-picking to release branches.

Fixes Piglit tests "unaligned-blit {2,4} stencil {msaa,upsample}" on
Sandy Bridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit a33ce665a5827c598b85bb04d94b33e6a5e41c28)
i965: Don't spill "smeared" registers.

Fixes an assertion failure when compiling certain shaders that need both
pull constants and register spilling:

brw_eu_emit.c:204: validate_reg: Assertion `execsize >= width' failed.

NOTE: This is a candidate for the 8.0 release branch.

Signed-off-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125)
i965/blorp: Add support for blits between SRGB and linear formats (fixed).

This is a squash of 2 commits from master.
The first commit is:

i965/blorp: Add support for blits between SRGB and linear formats.

Fixes colorspace issues in L4D2 when multisampling is enabled (the
scene was far too dark, but the flashlight area was way too bright).

The nVidia and AMD binary drivers both allow this kind of blit.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff)

The second commit is:

i965/blorp: Fix sRGB MSAA resolves.

Commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff (i965/blorp: Add
support for blits between SRGB and linear formats) changed blorp to
always configure surface states for in linear format (even if the
underlying surface is sRGB).  This allowed sRGB-to-linear and
linear-to-sRGB blits to occur without causing the image to be
inappropriately brightened or darkened.

However, it broke sRGB MSAA resolves, since they rely on the
destination buffer format being sRGB in order to ensure that samples
are averaged together in sRGB-correct fashion.

This patch fixes the problem by instead configuring the source buffer
to use the *same* format as the destination buffer.  This ensures that
the image won't be brightened or darkened, but preserves proper sRGB
averaging.

Fixes piglit tests "EXT_framebuffer_multisample/accuracy srgb".

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55265

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 124b214f094fa63ff1ddb7e9f0a1c2e0ba8214fb)