Fixed few warnings; trimmed empty lines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160159 91177308-0d34-0410-b5e6-96231b3b80d8
Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160162 91177308-0d34-0410-b5e6-96231b3b80d8
Restrict this to x86, hopefully fixing ARM buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160163 91177308-0d34-0410-b5e6-96231b3b80d8
Post-dom frontier was removed in 3.0.  Patch by chenwj.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160166 91177308-0d34-0410-b5e6-96231b3b80d8
ReleaseNotes.html: add note about specifying TLS models

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160168 91177308-0d34-0410-b5e6-96231b3b80d8
Initializers for some fields were missing in Option::Option


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160170 91177308-0d34-0410-b5e6-96231b3b80d8
Make helper functions static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160173 91177308-0d34-0410-b5e6-96231b3b80d8
test case for revision 160084: Alignment filling between Mips function units

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160177 91177308-0d34-0410-b5e6-96231b3b80d8
The Mips specific relocation R_MIPS_GOT_DISP 
is used in cases where global symbols are 
directly represented in the GOT and we use an 
offset into the global offset table.

This patch adds direct object support for R_MIPS_GOT_DISP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183 91177308-0d34-0410-b5e6-96231b3b80d8
Remove variable_ops from ARM call instructions.

Function argument registers are added to the call SDNode, but
InstrEmitter now knows how to make those operands implicit, and the call
instruction doesn't have to be variadic.

Explicit register operands should only be those that are encoded in the
instruction, implicit register operands are for extra dependencies like
call argument and return values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160188 91177308-0d34-0410-b5e6-96231b3b80d8
Remove variable_ops from call instructions in most targets.

Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed few warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160192 91177308-0d34-0410-b5e6-96231b3b80d8
Use the LiveVariables information to efficiently get local kills. This
removes the largest scaling problem in the test cases from PR13225 when
ASan is switched to insert basic blocks in the natural CFG order.

It may also solve some scaling problems for more normal code with large
numbers of basic blocks and variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160194 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r160194, which switched to use LV information for finding local
kills.

This is causing miscompiles that I'm working on tracking down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160196 91177308-0d34-0410-b5e6-96231b3b80d8
This is one of the first steps at moving to replace target-dependent 
intrinsics with target-indepdent intrinsics.  The first instruction(s) to be 
handled are the vector versions of count leading zeros (ctlz).

The changes here are to clang so that it generates a target independent 
vector ctlz when it sees an ARM dependent vector ctlz.  The changes in llvm 
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp 
to update any existing bc files containing ARM dependent vector ctlzs with 
target-independent ctlzs.  There are also changes to an existing test case in 
llvm for ARM vector count instructions and a new test for the bitcode upgrade.

<rdar://problem/11831778>

There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160200 91177308-0d34-0410-b5e6-96231b3b80d8
Factor SCEV traversal code so I can use it elsewhere. No functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160203 91177308-0d34-0410-b5e6-96231b3b80d8
IVUsers should only generate SCEV's for values that are safe to speculate.

This allows SCEVExpander to run on the IV expressions.

This codifies an assumption made by LSR to complete the fix for
PR11356, but I haven't been able to generate a separate unit test for
this part. I'm adding it as an extra safety check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160204 91177308-0d34-0410-b5e6-96231b3b80d8
LSR Fix: check SCEV expression safety before expansion.

All SCEV expressions used by LSR formulae must be safe to
expand. i.e. they may not contain UDiv unless we can prove nonzero
denominator.

Fixes PR11356: LSR hoists UDiv.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160205 91177308-0d34-0410-b5e6-96231b3b80d8
Be more verbose when detecting dominance problems.

Catch uses of undefined physregs that haven't been added to basic block
live-in lists. Run the verifier to pinpoint the problem.

Also run the verifier when a virtual register use is not jointly
dominated by defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160207 91177308-0d34-0410-b5e6-96231b3b80d8