MIPS: add register definition for EBase register

The CPUNum field in the Ebase register contains an unique identifier
for each CPU. This helps to distinguish between CPU cores in
multi-processor systems.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: extend cache initialization for recent MIPS CPU cores

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: refactor reset and exception vector setup

Use assembler macros for vector and handler setup.
Only implement the specific vectors offsets and let the
assembler fill the gap with zeroes.

Add missing exception vectors and handlers for Interrupt, CauseIV and
EJTAG debug.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: add init hook for CPU specific initialization

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: board.c: optimize error message string

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: simulate -ffunction-sections for assembler functions

Move all functions declared with LEAF or NESTED into an own
text section to allow garbage collecting of unused sections
for those functions.

This saves additional text space if functions like those in
cache.S are not used.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: start.S: add option for disabling cache on startup

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
cfi_flash: add optional and board-specific address swapping for CFI commands

This patch adds the possibility to (optionally) swap the address
in the flash_map function.

This is needed for the upcoming support of Lantiq SoCs which access
NOR flash over a little-endian AMBA bus whereas the MIPS CPU itself
operates in big-endian mode. To allow CFI probing and booting from
NOR flash, manual address swapping in software is needed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Merge branch 'next/switchlib' into HEAD
MIPS: lantiq: add initial support for Lantiq SoCs

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: lantiq: add support for Lantiq XWAY Danube family

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: serial: lantiq: add driver for UART found on Lantiq SoCs

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: dma: lantiq: add driver for DMA engine found on Lantiq SoCs

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: net: lantiq: add ethernet driver for Lantiq XWAY Danube SoC

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: SPI: lantiq: add driver for SPI found on Lantiq SoCs

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
MIPS: lantiq: easy50712: add board support for Lantiq EASY50712 Danube Reference board

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: Gigaset: sx76x: add board support for Gigaset SX76X

Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
net: phylib: fix phylib init for archs with manual relocation

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Andy Fleming <afleming@freescale.com>
MIPS: lantiq: add support for Lantiq XWAY VRX200 family

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
MIPS: VRX200: add support for internal GPHYs

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>