target-arm: Convert cp15 VA-PA translation registers

Convert the cp15 VA-PA translation registers (a subset of
the crn=7 regs) to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert cp15 crn=7 registers

Convert the cp15 crn=7 registers to the new scheme.
Note that to do this we have to distinguish some registers
used on the ARM9 and ARM10 from some which are ARM1176
only. This is because the old code returned a value of 0
but always set the Z flag (by clearing env->ZF, since we
store the Z flag in CPUState inverted). This is inconsistent
with actual ARM CPU behaviour, which only sets flags for
reads to r15 and sets them based on the top bits of the result.
However it happened to work for the two common use cases for
cp15 crn=7 reads:
 * On ARM9 and ARM10 the cache clean-and-test operations are
typically done with a destination of r15 so that you can do
a "loop: mrc ... ; bne loop" to keep cleaning until the cache
is finally clean; always setting the Z flag means this loop
terminates immediately
 * on ARM1176 the Cache Dirty Status Register reads as zero
if the cache is dirty; returning 0 means this is correctly
implemented for QEMU

Since the new coprocessor register framework does the right
thing of always setting flags based on the returned result
for reads to r15, we need to split these up so that we can
return (1<<30) for the ARM9/ARM10 registers but 0 for the
ARM1176 one.

This allows us to remove the nasty hack which always sets Z.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert cp15 crn=6 registers

Convert the cp15 crn=6 registers to the new scheme.
Note that this includes some minor tidyup: drop an unnecessary
underdecoding of op2 on OMAPCP cores, and only implement the
pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5
cores, which didn't have it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert cp15 crn=9 registers

Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.

Note that this change makes OMAPCP cores RAZ/WI the whole c9 space.  This is
a change from previous behaviour, but a return to the behaviour of commit
c3d2689d when OMAP1 support was first added -- subsequent commits have
clearly accidentally relegated the OMAPCP RAZ condition to only a subset of
the crn=9 space when adding support for other cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert cp15 crn=1 registers

Convert the cp15 crn=1 registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert cp15 crn=0 crm={1,2} feature registers

Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert cp15 cache ID registers

Convert the cp15 cache ID registers to the new scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert MPIDR

Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert final ID registers

Convert the final ID registers to the new cp15 scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Remove c0_cachetype CPUARMState field

Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Move block cache ops to new cp15 framework

Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Remove remaining old cp15 infrastructure

There are now no uses of the old cp15 infrastructure,
so it can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Remove ARM_CPUID_* macros

All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
ehci: add live migration support

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
usb: restore USBDevice->attached on vmload

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
ehci: tracing improvements

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
usb-host: attach only to running guest

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
usb-host: live migration support

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
uhci: fix uhci_async_cancel_all

We update the QTAILQ in the loop, thus we must use the SAFE version
to make sure we don't touch the queue struct after freeing it.

https://bugzilla.novell.com/show_bug.cgi?id=766310

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
xen: Reorganize includes of Xen headers.

Because xs.h will be remove in future release of Xen, this patch removes the
extra includes of this headers.

Also, it removes the extra includes of xenctrl.h and xen/io/xenbus.h as there
already are in xen_common.h.

Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>