controller のステートマシンに送信ステート列を追加
sd_cont をテストする用の top を作成
sd_cont のデバッグ

データ送信開始前に 1 byte の時間を空けなければいけないと書いてあるが、空けると先頭にゴミデータがつくので入れない。
キャッシュマネージャを write に対応
[from now] Sat Dec 15 14:25:40 JST 2012

diff --git a/2nd/mimic.v b/2nd/mimic.v
index 54c0abf..b7827f4 100644
--- a/2nd/mimic.v
+++ b/2nd/mimic.v
@@ -22,9 +22,11 @@ module mimic(input clk,
              input [7:0]   key_status,
              input [7:0]   keycode,

-             input [7:0]   sd_data,
+             input [7:0]   sd_read_data,
+             output [7:0]  sd_write_data,
              output [31:0] sd_addr,
-             output        sd_go,
+             output        sd_read,
+             output        sd_write,
              input         sd_ready);

    wire [15:0] inst_address, inst_write_address;
@@ -175,9 +177,11 @@ module mimic(input clk,
        .data(write_data_sd),
        .float(write_float_sd),

-       .sd_data(sd_data),
+       .sd_read_data(sd_read_data),
+       .sd_write_data(sd_write_data),
        .sd_addr(sd_addr),
-       .sd_go(sd_go),
+       .sd_read(sd_read),
+       .sd_write(sd_write),
        .sd_ready(sd_ready));

    assign write_enable_misc = write_enable_rs == 1'b1       ? write_enable_rs :
diff --git a/2nd/top.vhd b/2nd/top.vhd
index 076d72a..4b4e096 100644
--- a/2nd/top.vhd
+++ b/2nd/top.vhd
@@ -70,10 +70,12 @@ architecture top of top is
 			key_status : in std_logic_vector(7 downto 0);
 			keycode    : in std_logic_vector(7 downto 0);

-			sd_data  : in std_logic_vector(7 downto 0);
-			sd_addr  : out std_logic_vector(31 downto 0);
-			sd_go    : out STD_LOGIC;
-			sd_ready : in STD_LOGIC);
+			sd_read_data  : in std_logic_vector(7 downto 0);
+			sd_write_data : out std_logic_vector(7 downto 0);
+			sd_addr       : out std_logic_vector(31 downto 0);
+			sd_read       : out STD_LOGIC;
+			sd_write      : out STD_LOGIC;
+			sd_ready      : in STD_LOGIC);
   end component;

   component sramc is
@@ -151,16 +153,18 @@ architecture top of top is

 	component sdcard is
 		port (
-			clk : in STD_LOGIC;
+			clk    : in STD_LOGIC;
 			sd_clk : out STD_LOGIC;
-			sd_ce : out STD_LOGIC;
+			sd_ce  : out STD_LOGIC;
 			sd_out : out STD_LOGIC;
-			sd_in : in STD_LOGIC;
+			sd_in  : in STD_LOGIC;

-			sd_data : out std_logic_vector(7 downto 0);
-			sd_addr : in std_logic_vector(31 downto 0);
-			sd_go : in STD_LOGIC;
-			sd_ready : out STD_LOGIC;
+			sd_read_data  : out std_logic_vector(7 downto 0);
+			sd_write_data : in std_logic_vector(7 downto 0);
+			sd_addr       : in std_logic_vector(31 downto 0);
+			sd_read       : in STD_LOGIC;
+			sd_write      : in STD_LOGIC;
+			sd_ready      : out STD_LOGIC;

 			debug : out std_logic_vector(7 downto 0));
 	end component;
@@ -186,9 +190,9 @@ architecture top of top is
 	signal keycode    : std_logic_vector(7 downto 0);

 	-- sd
-	signal sd_data : std_logic_vector(7 downto 0);
+	signal sd_read_data, sd_write_data : std_logic_vector(7 downto 0);
 	signal sd_addr : std_logic_vector(31 downto 0);
-	signal sd_go, sd_ready : STD_LOGIC;
+	signal sd_read, sd_write, sd_read : STD_LOGIC;

 	signal debug : std_logic_vector(7 downto 0);

@@ -228,10 +232,12 @@ begin  -- test
 		key_status => key_status,
 		keycode    => keycode,

-		sd_data  => sd_data,
-		sd_addr  => sd_addr,
-		sd_go    => sd_go,
-		sd_ready => sd_ready);
+		sd_read_data  => sd_read_data,
+		sd_write_data => sd_write_data,
+		sd_addr       => sd_addr,
+		sd_read       => sd_read,
+		sd_write      => sd_write,
+		sd_ready      => sd_ready);

   i232c_buffer_inst : i232c_buffer port map (
     clk      => iclk,
@@ -288,10 +294,12 @@ begin  -- test
 		 sd_out   => SD_DO,
 		 sd_in    => SD_DI,

-		 sd_data  => sd_data,
-		 sd_addr  => sd_addr,
-		 sd_go    => sd_go,
-		 sd_ready => sd_ready,
+		 sd_read_data  => sd_read_data,
+		 sd_write_data => sd_write_data,
+		 sd_addr       => sd_addr,
+		 sd_read       => sd_read,
+		 sd_write      => sd_write,
+		 sd_ready      => sd_ready,

 		 debug => debug);
TO SYNTHESIZE

Conflicts:
	2nd/instruction/instruction_memory.v
[from now] Sat Dec 15 14:27:24 JST 2012

diff --git a/2nd/sdcard/sdcard.v b/2nd/sdcard/sdcard.v
index aec36dc..e1bf2d1 100644
--- a/2nd/sdcard/sdcard.v
+++ b/2nd/sdcard/sdcard.v
@@ -22,7 +22,7 @@ module sdcard(input clk,

    wire sd_read_spi, sd_write_spi;

-   assign debug = {4'b0, sd_go, sd_busy, sd_controller_go, sd_ready};
+   assign debug = 0;

    sd_cont sd_cont_inst
       (.clk(clk),
diff --git a/2nd/top.vhd b/2nd/top.vhd
index df5081e..30f3fb4 100644
--- a/2nd/top.vhd
+++ b/2nd/top.vhd
@@ -192,7 +192,7 @@ architecture top of top is
 	-- sd
 	signal sd_read_data, sd_write_data : std_logic_vector(7 downto 0);
 	signal sd_addr : std_logic_vector(31 downto 0);
-	signal sd_read, sd_write, sd_read : STD_LOGIC;
+	signal sd_read, sd_write, sd_ready : STD_LOGIC;

 	signal debug : std_logic_vector(7 downto 0);
[from now] Sat Dec 15 14:40:55 JST 2012

diff --git a/2nd/sdcard/sdcard.v b/2nd/sdcard/sdcard.v
index e1bf2d1..298fc93 100644
--- a/2nd/sdcard/sdcard.v
+++ b/2nd/sdcard/sdcard.v
@@ -22,7 +22,8 @@ module sdcard(input clk,

    wire sd_read_spi, sd_write_spi;

-   assign debug = 0;
+   wire [9:0] debug_out;
+   assign debug = debug_out[9:2];

    sd_cont sd_cont_inst
       (.clk(clk),
@@ -39,7 +40,9 @@ module sdcard(input clk,
        .sd_addr(sd_block),
        .sd_read(sd_read_spi),
        .sd_write(sd_write_spi),
-       .sd_busy(sd_busy));
+       .sd_busy(sd_busy),
+
+       .debug(debug_out));

    sd_cache sd_cache_inst
       (.clk(clk),