Add instcombine patterns for the following transformations:

 (x & y) | (x ^ y) -> x | y 
 (x & y) + (x ^ y) -> x | y 

Patch by Manman Ren.
rdar://10770603


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155674 91177308-0d34-0410-b5e6-96231b3b80d8
Turn IVChain into a struct.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155675 91177308-0d34-0410-b5e6-96231b3b80d8
Break up getProfitableChainIncrement().

The required checks are moved to ChainInstruction() itself and the
policy decisions are moved to IVChain::isProfitableInc().

Also cache the ExprBase in IVChain to avoid frequent recomputations.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155676 91177308-0d34-0410-b5e6-96231b3b80d8
Use ConstantExpr::getExtractElement when constant-folding vectors
instead of getAggregateElement. This has the advantage of being
more consistent and allowing higher-level constant folding to
procede even if an inner extract element cannot be folded.

Make ConstantFoldInstruction call ConstantFoldConstantExpression
on the instruction's operands, making it more consistent with 
ConstantFoldConstantExpression itself. This makes sure that
ConstantExprs get TargetData-aware folding before being handed
off as operands for further folding.

This causes more expressions to be folded, but due to a known
shortcoming in constant folding, this currently has the side effect
of stripping a few more nuw and inbounds flags in the non-targetdata
side of constant-fold-gep.ll. This is mostly harmless.

This fixes rdar://11324230.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155682 91177308-0d34-0410-b5e6-96231b3b80d8
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
  instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
Implement a bastardized ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
Add mcpu to tests to prevent them from using AVX instructions on Sandy Bridge after r155618.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696 91177308-0d34-0410-b5e6-96231b3b80d8
[tsan] Atomic support for ThreadSanitizer, patch by  Dmitry Vyukov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155698 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r155682, "Use ConstantExpr::getExtractElement when constant-folding vectors"

It broke stage2 build. stage1/clang sometimes crashed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155699 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
[asan] small optimization: do not emit "x+0" instructions 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155701 91177308-0d34-0410-b5e6-96231b3b80d8
Update config.sub in the sample project.

This change replaces projects/sample/autoconf/config.sub with a copy of
autoconf/config.sub.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155703 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.

* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.

Fixes PR6679. Patch by Christoph Erhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
Update edis test for r155704.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155705 91177308-0d34-0410-b5e6-96231b3b80d8
Missed some register numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155706 91177308-0d34-0410-b5e6-96231b3b80d8
Remove a docs reference to the CBackend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155716 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ARM assembly parsing for upper case condition codes on IT instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r155682, making constant folding more consistent, with a fix to work
properly with how the code handles all-undef PHI nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155721 91177308-0d34-0410-b5e6-96231b3b80d8
Add an early bailout to IsValueFullyAvailableInBlock from deeply nested blocks.
The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow
issues. <rdar://problem/11286839>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155722 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/11325085>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8