OMAPDSS: DISPC: Fix rounding error in scaling decision

When checking if we are downscaling by more than a factor,
we were dividing the source dimensions instead of multiplying
back the target dimensions.  This allowed downscaling by
slightly more than the max supported downscaling, resulting
in out-of-range register settings and ultimately SYNC_LOST.

Change-Id: Ic039789c5011d64da870121eeb227a803af1fa83
Signed-off-by: Lajos Molnar <lajos@ti.com>
OMAP4: PM: errata: Wkup clk recycling needed after warm reset.

As W/A the call to omap4_trigger_ioctrl() has been added
at PM initialization time for I/O pads daisy chain reseting.

TI EID: i612; IMPACTED: OMAP4430 all revisions

Change-Id: Ifff5cf4ed79e15bbeed97dd2b1cc7d7cf19d2387
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Conflicts:

	arch/arm/mach-omap2/pm44xx.c
OMAP4: PM: Add errata id for handling Errata i736

The errata handler is present in kernel 3.0. The patch adds the
Errata id for simplification of search in the kernel sources

Change-Id: I346ac0e1262fdb3fcfd1e38879619baa02ebf4cb
Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>

Conflicts:

	arch/arm/mach-omap2/pm44xx.c
OMAP4: PM: Add errata id for handling Errata i745

The errata handler is present in kernel 3.0. The patch adds the
Errata id for simplification of search in the kernel sources

Change-Id: I251c0bd09754e5af9ec40c01c50e24e25eba9227
Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>

Conflicts:

	arch/arm/mach-omap2/pm44xx.c
OMAP4: PM: IVA AUTO RET relaxed workaround in idle path

AUTO RET for IVA VDD Cannot be permanently enabled during OFF mode due to
potential race between IVA VDD entering RET and start of Device OFF mode.

It is mandatory to have AUTO RET for IVA VDD exlusive with Devide OFF mode.
In order to avoid lockup in OFF mode sequence, system must ensure IVA
voltage domain transitions straight from stable ON to OFF.

In addition, management of IVA VDD SmartReflex sensor at exit of idle path
may introduce a misalignment between IVA Voltage Controller state and IVA
PRCM voltage FSM based on following identified scenario:

IVA Voltage Controller is woken-up due to SmartReflex management while
IVA PRCM voltage FSM stays in RET in absence of any IVA module wake-up event
(which is not systematic in idle path as opposed to MPU and CORE VDDs being
necessarily woken up with MPU and CORE PDs).

WA involves:
Ensure stable ON-OFF transition for IVA voltage domain during OFF mode sequence.
Ensure VCON and PRCM FSM are kept aligned due to IVA SR handling in idle path.
1) AUTO RET for IVA VDD is enabled entering in idle path, disabled exiting idle
   path and IVA VDD is always woken-up with a SW dummy wakeup.
2) OFF mode is enabled only in Suspend path.
3) AUTO RET for IVA VDD remains disabled in Suspend path (before OFF mode).

REVISIT: Update the patch once proper Errata is out for 44xx.

Benefits:
1) This patch ensures it is possible to gate SYS_CLK during OS-Idle LCD OFF
when all domains are idled, saving up to 2mA at VBAT from external clock buffer.

2) IVA voltage domain is now allowed to scale to Retention during idle which
reduces power consumption on all types of use case allowing extensive use of
idle path (e.g.: Home screen, Page reading). Effects are especially visible
if system uses Smart-Reflex Class 1.5 compared to Class 3 considering the
increased difference of voltage from converged Voltage SR vs Retention voltage.

TODO: quantify the actual savings from IVA-RET with further measurements.

Change-Id: I01f0431f7556f0baf0b5b6b42092cd11c2442f00
Signed-off-by: Cedric Vamour <c-vamour@ti.com>
Fix cherry-pick fail
Raise VUSIM and VAUX3 voltages for staility