Move AVX version of convert instructions that write to GPRs to the Op1 table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158497 91177308-0d34-0410-b5e6-96231b3b80d8
Fix issues (infinite loop and/or crash) with self-referential instructions, for
example degenerate phi nodes and binops that use themselves in unreachable code.
Thanks to Charles Davis for the testcase that uncovered this can of worms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158508 91177308-0d34-0410-b5e6-96231b3b80d8
Free the allocated filename. Found by clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158513 91177308-0d34-0410-b5e6-96231b3b80d8
Factor macro argument parsing into helper methods and add support for .irp.
Patch extracted from a larger one by the PaX team. I added the testcases
and tightened error handling a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158523 91177308-0d34-0410-b5e6-96231b3b80d8
Use regunit liveness in RegisterCoalescer when it is available.

We only do very limited physreg coalescing now, but we still merge
virtual registers into reserved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158526 91177308-0d34-0410-b5e6-96231b3b80d8
Preserve <undef> flags in ARMExpandPseudo.

This probably mostly shows up in bugpoint-generated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158527 91177308-0d34-0410-b5e6-96231b3b80d8
Some optimizations done by globalopt are safe only for internal linkage, not
linkonce linkage. For example, it is not valid to add unnamed_addr.

This also fixes a crash in g++.dg/opt/static5.C.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158528 91177308-0d34-0410-b5e6-96231b3b80d8
Allow SROA to split up an array of vectors into multiple vectors, even when the vectors are dynamically indexed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158529 91177308-0d34-0410-b5e6-96231b3b80d8
Remove assignments which aren't used afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158534 91177308-0d34-0410-b5e6-96231b3b80d8
Remove assignments which aren't used afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158535 91177308-0d34-0410-b5e6-96231b3b80d8
LSR fix: "Special" users are just like "Basic" users but allow -1 scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158536 91177308-0d34-0410-b5e6-96231b3b80d8
LSR: fix expansion of scaled reg in non-address type formulae.

For non-address users, Base and Scaled registers are not specially
associated to fit an address mode, so SCEVExpander should apply normal
expansion rules. Otherwise we may sink computation into inner loops
that have already been optimized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158537 91177308-0d34-0410-b5e6-96231b3b80d8
*fixed to separate mnemonic from operands with tab

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158543 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: optimization for sub+abs.

This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi

For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.

rdar: 11633193


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Make it pretty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158561 91177308-0d34-0410-b5e6-96231b3b80d8
Accept null PhysReg arguments to checkRegMaskInterference.

Calling checkRegMaskInterference(VirtReg) checks if VirtReg crosses any
regmask operands, regardless of the registers they clobber.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158563 91177308-0d34-0410-b5e6-96231b3b80d8
Unit test for LSR kind=Special fix: r158536.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158570 91177308-0d34-0410-b5e6-96231b3b80d8
Print out register number in InlineSpiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158575 91177308-0d34-0410-b5e6-96231b3b80d8
Remove final verification in RABasic.

We now have a proper machine code verifier pass between register
allocation and rewriting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158577 91177308-0d34-0410-b5e6-96231b3b80d8