msm: acpuclock-8x60: Drop "slowest" frequency table

The voltage data in this table is not used. It applied only to
a handful of internal part samples that were never distributed.
Remove it, since it is neither maintained nor useful.

Change-Id: I2a08bd0287a400cfb65666dc3445fd5441d784d1
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: acpuclock-8x60: Optimize CPU voltages on 1.7GHz parts

Hardware characterization shows that these parts can operate reliably
at lower voltages than were previously used. Update the tables to
take advantage of the power savings.

Change-Id: I6aca2da89e343c1588579e7183a0ce375cb9a821
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: acpuclock: Fix error path in multicore targets

Several acpuclock drivers have inherited the same error path bug in
acpuclk_set_rate(). If an invalid cpu is passed as an argument to
these functions, they should return immediately instead of jumping to
the 'out' label, which attempts to unlock a mutex which has never
been acquired.

Change-Id: I47b9709605673a5200caf73a2f2a5086fde63efe
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm_fb: Fix error in y-offset check logic in FB driver

After 4 KB alignment changes, the frame from 3rd buffer doesn't
get updated since during PUT_VSCREEN_INFO ioctl, the driver
returns -1 to userspace due to error in logic because the hole
size is not considered in calculating the logic for validity of
the y-offset. Change fixes this error.

CRs-fixed: 325134
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
(cherry picked from commit d37b52404236bf4cadf530a238cafc5d6499d32a)

Change-Id: Ifccfa25a37fe0f8d86bf5b822d9affe7fa41203a
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
msm_fb: Clean up the fix for error in y-offset check in FB driver

There is a failure observed in yres_virtual offset check and every
third frame gets skipped without an error message. Due to this high
fps is noticed in the test applications. Correct the yres_virtual
offset check.

CRs-fixed: 325134
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
(cherry picked from commit 2bd101d5bed1729b317114456360605e86289c15)

Change-Id: I35af570df2d6d2609562203f30f3caa1506b9b1d
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
video: msm: Allow PCC/GC to be disabled/select bins

Current implementation would not set enable/disable bits to PCC/GC nor be
able to select the zero'th bin after selecting the first.

CRs-Fixed: 345395
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
(cherry picked from commit 59e7b0e47eaee57850157361f31c230b3e1c8a8f)

Change-Id: I2ee5d485f0cc32e7d0286aefff00bd3b3dcaa482
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
arm: show present cpu instead of online cpu in /proc/cpuinfo

Some userspace applications use /proc/cpuinfo to determine how many CPUs
the system has. CPU hotplug can offline a CPU at runtime and causing the
offline CPU not present in /proc/cpuinfo if we only show online cpu in
/proc/cpuinfo.

CRs-Fixed: 354430
Signed-off-by: Jin Hong <jinh@codeaurora.org>
(cherry picked from commit 1e28794d0ff00fc6567d68b5b4e863b0745cfe20)

Change-Id: I3b38472b690bb3dba67ada74f60cce79ed0b2a7d
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
USB: f_mtp: Fix corner cases in MTP driver while syncing

Currently if USB composition switch happens while file transfer is
happening either from/to device, ep_queue fails and sets device state
to ERROR even if device state is already set to OFFLINE in function
disable call.

As part of ioctl call, if the state is not offline, moving the device
state to READY and returning the error. Since the device state is marked
as READY, the next write call tries to queue the request to hardware and
is blocked and due to this, userspace is not calling the release function.
Hence next mtp open fails even after cable reconnection.

CRs-Fixed: 360409
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
(cherry picked from commit 0097223c586963c9904c90803eaa5ee878565fbe)

Change-Id: I9d11cfd44f98a4fcf4e95f75462904bfb2b6cb2d
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: clock-8960/8660: Support 32/64MHz prng clock frequency plan

Add support for both the 32MHz and the 64MHz prng frequencies.
Some bootloaders configure the PRNG to 32MHz and others choose
64MHz. Support both so that we always vote for the correct
voltage

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 842a1f6b0eb8ecf40f97fa020fa004745ba1ab48)

Conflicts:

	arch/arm/mach-msm/clock-8960.c
	arch/arm/mach-msm/clock-8x60.c

Change-Id: I732aaa78d2019d6fefd90456f67ca27db1be9874
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm_fb: display: Add pre-multiplied alpha support for MDP4.

MDP4 blend logic differs from GPU blend implementation as MDP4
does not differentiate between pre-multiplied alpha layers and
non pre-multiplied alpha layers. Check layers for pre-multiplied
alpha and change blend logic accordingly.

CRs-Fixed: 355755
CRs-Fixed: 361729
Change-Id: Id8253d3888f1ebbadba1b6bbd87e7d98bac22da7
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm: gic: Remove manual GIC programming for PPI trigger type

There is no need to manually program GIC for edge trigger PPIs
through board or device file hooks after the introduction of
enable_percpu_irq(.., type) interface. 2nd parameter of this
API needs to be used for programming the right trigger
type for the PPI.

Change-Id: Ie200928eb70fcbab6646ddd63acfd89a1a87f5fe
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
panic: Fix a possible deadlock in panic()

panic_lock is meant to ensure that panic processing takes
place only on one cpu; if any of the other cpus encounter
a panic, they will spin waiting to be shut down.

However, this causes a regression in this scenario:

1. Cpu 0 encounters a panic and acquires the panic_lock
   and proceeds with the panic processing.
2. There is an interrupt on cpu 0 that also encounters
   an error condition and invokes panic.
3. This second invocation fails to acquire the panic_lock
   and enters the infinite while loop in panic_smp_self_stop.

Thus all panic processing is stopped, and the cpu is stuck
for eternity in the while(1) inside panic_smp_self_stop.

To address this, disable local interrupts with
local_irq_disable before acquiring the panic_lock. This will
prevent interrupt handlers from executing during the panic
processing, thus avoiding this particular problem.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
(cherry picked from commit dd58afef43357f265e803c317bbaa91f8c440663)

Change-Id: I5f7ebcf2a028df265a57922b6c959e686a82026a
Signed-off-by: Swetha Basineni <sbasin@codeaurora.org>
Perf: Dont reset PMU's if perf is not active

Perf would save and restore counters after resetting the PMU when
the CPU's came out of power collapse even if a perf session wasn't
active. Check if perf was running before going into power collapse
and only then reset PMU's while coming out.

This way PMU's can be accessed externally via the RPM or T32 without
perf intruding in counter output.

Change-Id: I33ac11b2a5cae21456341fde015aabe5b4bb8f52
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
arm: gic: Register irqdomain after adding it

Recently a change was added to break apart irq_domain_add() into
two functions. The first creates the domain, and the second
registers it.

This change abides to this new interface and registers the
GIC irq_domain after creating it.

Change-Id: I34c6a1f56dc27113a9b72f0fefa577276f91bbc8
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Check for error code on irq_domain_add

This API now returns an error. Since gic_init_bases() is called
early on, there's probably not a whole lot we can do here except
send a warning.

Change-Id: I2835dacfa191db0ce70434de23e6ee540fe33b57
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
arm: gic: Configure the GIC to run in secure mode

Configure the GIC to run in secure mode and handle
secure as well as non-secure interrupts. This patch
adds an API to configure an IRQ as a secure IRQ so that
it can be treated as an FIQ in the secure mode.

Change-Id: Ic3321e76c95a4c10d6287ba418e84623e7004cb1
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
ARM: gic: Add support to access GIC in secure mode

Currently gic secure mode is enabled for all the v7 cpus.
For 8x25 we do not want to access GIC in secure mode as
we are observe issues of not able to clear the pending clear
registers when we come out of power collapse.

The Kconfig should make it flexible for targets who want to
support GIC in secure/non-secure modes.

Change-Id: Id7c85f5b741346233993966752607e5c4fb23e74
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625

On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.

Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.

Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.

AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................

As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.

CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
ARM: gic: Move GIC based code out from mpm-8625

Moving code which modifies the GIC registers. As there is no global
lock in gic code, moving the code out.

Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/mpm-8625.c
	arch/arm/mach-msm/platsmp-8625.c
ARM: gic: protect some of 8625 GIC functionality with irq spinlocks

msm_gic_spi_ppi_pending, msm_gic_save and core1_gic_configure_and_raise
gets called with interrupt enabled on the core0, so it is possible
that we get into the spinlock deadlock since interrupt like timer PPI
could get fired on core0 and get locked in gic_handle_irq() routine
itself, so move these spinlocks to irqsave variants to avoid this
scenario.

CRs-Fixed: 363249
Change-Id: I2d40d6e26f5d9dba4ee6b9d4602cd0e685226693
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>