Revert "msm_fb: Clean up of frame buffer 4KB alignment changes"

This reverts commit c9b0b0db6628f6fc3fd863b46fafd89cb7dc92cb.
msm_fb: Make buffers aligned to 4K page boundary

This change makes the frame buffers aligned to the page
boundary. Improves GPU performance since accessing the
frame buffer from page boundary is faster.

CRs-fixed: 325134
Change-Id: I6ce4477f62536a3cd81064e26dc08f2b199e181b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/board-msm7627a-display.c
	drivers/video/msm/mdp4_overlay_atv.c
	drivers/video/msm/mdp4_overlay_dsi_video.c
	drivers/video/msm/mdp4_overlay_lcdc.c
	drivers/video/msm/mdp_dma.c
	drivers/video/msm/mdp_dma_lcdc.c
	drivers/video/msm/msm_fb.c
msm_fb: Clean up of frame buffer 4KB alignment changes

Remove redundant code from the 4 KB alignment patch
and reduce the overhead of calculation of the hole
size by using bitwise operators in its calculation.

CRs-fixed: 325134
Change-Id: Ie2e3ea7cbb2a815ae4f50cb97e6c5be1bd72fe27
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay_dsi_video.c
	drivers/video/msm/mdp_dma_lcdc.c
msm_fb: Fix error in y-offset check logic in FB driver

After 4 KB alignment changes, the frame from 3rd buffer doesn't
get updated since during PUT_VSCREEN_INFO ioctl, the driver
returns -1 to userspace due to error in logic because the hole
size is not considered in calculating the logic for validity of
the y-offset. Change fixes this error.

Change-Id: Ib151970eacab4df36fb8274be0079bc814e93efe
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: display: remove #if 0

Cleanup all #if 0s in display driver.

Change-Id: I32473b33ad4dff3e5d3d91aae42d70955836cd52
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
msm_fb: display: disable pan display and memory access to fb1 and fb2

The native fb1 and fb2 framebuffer memory is not used and not
allocated on the board file. So on the driver side, pan display ioctl
or other operations on fb1 or fb2 framebuffer memory is checked and
invalidated.

CRs-fixed: 357242
Change-Id: I2883926251a0465f69f18c442d5867556a4651bf
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>

Conflicts:

	drivers/video/msm/msm_fb.c
msm_fb: display: Move mipi dsi clock enable before dsi soft reset

mipi_dsi_clk_enable() is called after dsi soft reset. Move mipi dsi clock
enable before dsi soft reset as per mipi dsi hardware design document.

Change-Id: Ie1cfdf53bc74b87b5a0e0679ab26bc513205673d
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
msm_fb: display: Fix invalid x offset programming for YUV444 fmt

Source x offset adjustment is not properly programmed for YUV444 format,
it is always programmed as 0. Add support for correct x offset
adjustment.

Change-Id: I73e87f961bda60670cc764c66be955e48ccf2734
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
msm_fb : Disable power collapse before VSync to negate wake up latencies.

For a 16ms frame period  the CPU may go into deep power collapse.
Based on the power collapse exit latency for that low power mode,
the frame period gets extended by the latency to wake up the CPU at the
next VSYNC. This results in a user experience glitch. Adding an hrtimer
to wake up the CPU few ms before the Vsync and disabling power collapse
compensates for the extra time spent in waking up the CPU out of deep
sleep. On timer expiry, set wakelock to veto idle power collapse till
the next VSync. The wakelock is released on the next VSYNC occurrence.

Change-Id: I3e013cc54c36d3015d6fafa4b9ccd435cb5532ab
Signed-off-by: Anitha Anand <anithas@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay_dsi_video.c
	drivers/video/msm/msm_fb.c
msm-fb: display: Perf changes for mdp composition

Display under-run issues are observed with mdp composition.
Fix underrun issues by changing perf level.

CRs-Fixed: 354377
Change-Id: I82346e65af173d7592506f1cee7f90f40ee01485
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>

Conflicts:

	drivers/video/msm/mdp4_overlay.c
msm_fb: Correct the chroma offset calculations for Yamato format

In the PPP blit operations, when the source image format is
Yamato, there is chroma offset calculations going wrong in
the case when a frame is split into parts and blit is done
separately. Correct the chroma offset calculations in this
case.

CRs-fixed: 366908
Change-Id: I867024632fda9f64a569150e0b6389d55614cd3a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: display: Enable MDP clock's overlay block during panel on

MDP clock's overlay block is enabled during first update after panel
on currently. This is now moved to panel on to keep clock enabled
right from display on time.

Signed-off-by: Ravishangar Kalyanam <rkalya@codeaurora.org>
Change-Id: Ie201186c1471201874f2eff246486bc4a73b5872
msm_fb: display: Configure MDP clock table based on DSI Video pixel clk

To avoid display underrun issues, configure the MDP clock table's rate
according to DSI Video mode panel's pixel clock frequency by 1.15 times.

Change-Id: I9bc864a754c2d51c9d86ece79863820eb72cdae8
Signed-off-by: Nagamalleswararao Ganji <nganji@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
msm_fb: display: add out of range check for display sizes

MDP pipe or mixer size registers have 12-bit number, so boundary
checks are needed for those parameters. If not, input req sizes could
be very large 32 bit unsigned numbers, e.g. 0xffffffff, unsigned
operations may have overflow to pass all later checks, causing MDP
underruns or hang issues.

CRs-fixed: 380469
Change-Id: I096d7022ede21d54266b46a140782ab0348dd54b
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>