gallivm: Re-add the kludge for lp_build_lerp of fixed point types.

I removed it in commit 7d44d354bdba853e453ce3991396e2b0933468f4 but
texture sample code still relies on it.

Not sure how to this cleanly, so put it pack for now.
i965/gen7: Add some safety checks for send messages from GRFs.
i965: Add a header_present flag for setting up dp read messages.

As of gen7, we can skip the header on some messages, and this can make
optimization on those messages much nicer when you've got GRFs instead of MRFs
as the source.
i965/fs: Rename the existing pull constant load opcode.

We're going to use another send message for handling loads with a varying
per-fragment array index.
i965/fs: Add instruction emit for varying-index reads of uniforms.

The gen7 send-from-GRF path is sufficiently different from the perspective of
IR generation and optimization that I just made it a separate opcode.

v2: fix whitespace, rebase on Ken's recent refactor.
i965/fs: Allow source mods on gen7+ math.

This gen6 restriction was removed in gen7 as the mathbox merge to act
more like a normal instruction was finished in the hardware.
i965/fs: Restrict optimization that would fail for gen7's SENDs from GRFs

v2: Fix SNB math bug in register_coalesce() where I was looking at the
    instruction to be removed, not the instruction to be copy propagated
    into.
i965/fs: Conditionalize constant-index UBO load code and add comments.

I wanted to separate this step for easier reviewing when I add the
variable-index case next.
i965/fs: Add support for uniform array access with a variable index.

Serious Sam 3 had a shader hitting this path, but it's used rarely so it
didn't show a significant performance difference (n=7).  It does reduce
compile time massively, though -- one shader goes from 14s compile time
and 11723 instructions generated to .44s and 499 instructions.

Note that some shaders lose 16-wide mode because we don't support
16-wide and pull constants at the moment (generally, things looping over
a few-element array where the loop isn't getting unrolled).  Given that
those shaders are being generated with 15-20% fewer instructions, it
probably outweighs the loss of 16-wide.
scons: Require drm to build gallium/state_trackers/egl/x11/x11_screen.c.

x11_screen.c includes xf86drm.h, which comes from libdrm-dev.

This patch fixes this build error.

  Compiling src/gallium/state_trackers/egl/x11/x11_screen.c ...
src/gallium/state_trackers/egl/x11/x11_screen.c:30:21: fatal error: xf86drm.h: No such file or directory

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
mesa: expose ARB_texture_cube_map_array in core contexts as well

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@gmail.com>
draw: set precalc_flat flag for AA lines too

Fixes flat shading for AA lines.  demos/src/trivial/line-smooth is a
test case which hits this.

Note: This is a candidate for the stable branches.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
glsl: add new variable declaration in function body in lower_output_read

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
r600g: Use default mul/mad function for tgsi-to-llvm

Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
gallivm: have a default emit function for fdiv/rcp

Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
r600g: use default action for fdiv/rcp opcode

Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
gallivm: Have a default emit function for min/max opcode

Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
r600g: use default action for min/max opcode in tgsi to llvm

Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
i965: Add a flag for instructions with normal writemasking disabled.

For getting values from the new timestamp register, the channels we
load have nothing to do with the pixels dispatched.
i965: Add a debug flag for counting cycles spent in each compiled shader.

This can be used for two purposes: Using hand-coded shaders to determine
per-instruction timings, or figuring out which shader to optimize in a
whole application.

Note that this doesn't cover the instructions that set up the message to
the URB/FB write -- we'd need to convert the MRF usage in these
instructions to GRFs so that our offsets/times don't overwrite our
shader outputs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)

v2: Check the timestamp reset flag in the VS, which is apparently
    getting set fairly regularly in the range we watch, resulting in
    negative numbers getting added to our 32-bit counter, and thus large
    values added to our uint64_t.
v3: Rebase on reladdr changes, removing a new safety check that proved
    impossible to satisfy.  Add a comment to the AOP defs from Ken's
    review, and put them in a slightly more sensible spot.
v4: Check timestamp reset in the FS as well.