Make the 'getAsString' function a method of the Attributes class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164305 91177308-0d34-0410-b5e6-96231b3b80d8
Specify cpu to get the correct instruction ordering. Remove XFAIL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164306 91177308-0d34-0410-b5e6-96231b3b80d8
Remove more bare uses of the different Attribute enums.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164307 91177308-0d34-0410-b5e6-96231b3b80d8
Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164308 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r164308 to fix buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164309 91177308-0d34-0410-b5e6-96231b3b80d8
Fix function names in coding style examples

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164311 91177308-0d34-0410-b5e6-96231b3b80d8
Fix broken check lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164317 91177308-0d34-0410-b5e6-96231b3b80d8
Try to make these tests more portable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164320 91177308-0d34-0410-b5e6-96231b3b80d8
SimplifyCFG: sink common codes from IF, ELSE blocks down to END block.

We already have HoistThenElseCodeToIf, this patch implements
SinkThenElseCodeToEnd. When END block has only two predecessors and each
predecessor terminates with unconditional branches, we compare instructions in
IF and ELSE blocks backwards and check whether we can sink the common
instructions down.

rdar://12191395


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164325 91177308-0d34-0410-b5e6-96231b3b80d8
Only emit DW_AT_object_pointer if this is a definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164326 91177308-0d34-0410-b5e6-96231b3b80d8
Extend -new-coalescer SSA update to handle mapped values as well.

The old-fashioned many-to-one value mapping doesn't always work when
merging vector lanes. A value can map to multiple different values, and
it can even be necessary to insert new PHIs.

When a value number is defined by a copy from a value number that
required SSa update, include the live range of the copied value number
in the SSA update as well. It is not necessarily a copy of the original
value number any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164329 91177308-0d34-0410-b5e6-96231b3b80d8
Ignore PHI-defs for -new-coalescer interference checks.

A PHI can't create interference on its own. If two live ranges interfere
at a PHI, they must also interfere when leaving one of the PHI
predecessors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164330 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Use a dedicated intrinsic for vector bitwise select.

The expression based expansion too often results in IR level optimizations
splitting the intermediate values into separate basic blocks, preventing
the formation of the VBSL instruction as the code author intended. In
particular, LICM would often hoist part of the computation out of a loop.

rdar://11011471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
Tidy up. Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164343 91177308-0d34-0410-b5e6-96231b3b80d8
Tidy up. Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164344 91177308-0d34-0410-b5e6-96231b3b80d8
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
non-halfword-aligned i16 loads/stores.
rdar://12304911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
Add newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164346 91177308-0d34-0410-b5e6-96231b3b80d8
Testcase does not need to be this strict.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164347 91177308-0d34-0410-b5e6-96231b3b80d8
Properly save and restore RA and Mips16 callee save registers S0,S1

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164349 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_store/@unaligned_i16_load/g.

I guess this had apparently passed in +Asserts possibly due to verborsity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164350 91177308-0d34-0410-b5e6-96231b3b80d8