OMAP4: clock: Reuse 4460 MPU clock for 4470

OMAP4470 has the same MPU clock scheme as OMAP4460.
Reuse virt_dpll_mpu_ck clock for 4470.

Change-Id: Id3f992d1595c5cc02d316199ad999a084f623b1f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: PM: powerdomain: Reuse 4460 MPU powerdomain for 4470

MPU powerdomain in OMAP4470 has the same characteristics as in OMAP4460.
So powerdomain stucture can be reused for 4470.

Change-Id: Ib18ae5f56b532a7ad5bdfaf67965fbe1ff5076e6
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: hwmod: Reuse 4460 HWMODs for 4470

A set of OMAP4470 harware modules is the same as in OMAP4460.
Reuse following HWMOD structures for 4470:
 - Control Module
 - Bandgap
 - Thermal sensor
 - GPIO1 bank

Change-Id: I247accdcddd06e32daad2e632830cbec2619373b
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4460: OPP: add recommended conservative s/w margins

Considering the delta from Class 3 to Class 1/1.5, a recalibration
delay of 1 week, and maximum operating temperature range,
update per OPP s/w margins as per conservative safe margins.

Further characterization is in progress to provide more optimized,
yet safe margins and these numbers are with the data collected
as of current time.

Change-Id: I6ae778ff541bc515636181efcbece44a73eb8f96
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: ID: Add runtime detection of 4470 1.5Ghz silicon

STD_FUSE_PROD_ID_1[17:16] fuse determines silicon type:
0x1 - Standard performance (1.3 GHz)
0x2 - High performance (1.5 GHz)

Change-Id: I7e37daf1d214d63b35f10fa45952485c59cbc009
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
configs: Add blaze_4470_defconfig

Adding blaze_4470_defconfig. The only difference from
blaze_defconfig is SGX core version. (SGX 544 on OMAP 4470).

Change-Id: I289b40221f3b424f1a759849db1e3a04a4be5a53
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
OMAP4: clock: Use DCC in 4470 for OPPs higher than 1GHz

OMAP4470 doesn't have a DCC issue so DCC can be used
for frequencies higher than 1GHz.

Change-Id: I76e8559b532264f01b51d7caa38ca294e8565834
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4470: OPP/voltage: Add voltage for OPPSB

OPPNT and OPPSB have the same voltage, but they should have different nTargets.
Wrong nTargets leads to instability at 1.5GHz, because voltage goes too low.

Change-Id: I698920118860cce47e76c5c03fa9c829c06454a2
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: OPP: Add High Performance CORE OPP set

OMAP4470 specification defines two sets of CORE OPPs:

   OPP  |    Low Power     | High Performance |
        | Volt | L3  | SGX | Volt | L3  | SGX |
--------+------+-----+-----+------+-----+-----+
 OPP50  | 0.96 | 100 | 154 | 0.96 | 117 | 191 |
 OPP100 | 1.13 | 200 | 307 | N/A  | N/A | N/A |
 OPP-OV | 1.23 | 200 | 384 | 1.23 | 233 | 384 |

High Performance set is enabled if CORE DPLL frequency is higher than 1600MHz.
OPP100 is absent in High Performance set.

Change-Id: Ief4c6617940365e18a0f5a22adf94a3c6f3b7192
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: clock: Extend L3 clock dependencies to cover 4470

Currently L3 OPP50 frequency is hardcoded to 100MHz.
But OMAP4470 has High Performance CORE OPP set where L3 OPP50 is 116MHz.
This patch exetends L3 clock dependencies to cover 4470 HP CORE OPP set.

Assumption made that DDRPHY freq is always 4x L3 freq.

Change-Id: I124b77d797c16ea0ccf32ba7b74a3d1c0bfe1058
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: EMIF: Added timings for 466MHz elpida lpddr2 memory

OMAP4470 support 466MHz DDR2 memory. This patch add timings from
datasheet for EDB8164B3PF.

Change-Id: Ief7520719a2d7ec3dc9c93a3ecbfcef7cf64507c
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
OMAP4: TEMP_SENSOR: Additional checking for context lost scenario

Calling pm_runtime_get_sync() function during driver initialization
leads to formation of the resume request, which will restore
registers values using not yet initialized data.

To prevent invalid data writing into registers at the early
stage of booting, additional checking has been added.

Change-Id: Ia14368ef1dd8430b8ba561bede0da7d46d9efb0e
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
OMAP4470: TEMP_SENSOR: Fatal threshold hardware warm reset generation

On 4470 the TSHUT signal can be mapped to the device SCRM external
warm reset logic to activate the PRM.SYS_WARMIN_RST input
when a fatal temperature threshold (TSHUT_HOT) is exceeded.
Hence, a hardware warm reset can be triggered directly on
the device upon a fatal temperature threshold crossing event.

Since this feature have been added for 4470, shutdown thresholds
can be set earlier. So, additional checking has been added to prevent
multiple writing to one time writable register.

Also this patch add corresponding sysfs debug hook functions to
enable/disable hardware reset feature.

Change-Id: I260e16e2808fddc0ecb06211a74aced8c4b12a5d
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
OMAP4: TEMP_SENSOR: Tuning values of TSHUT-thresholds

Based on OMAP4460 experiment, it is safer to set values of the
TSHUT_HOT and TSHUT_COLD thresholds to 100 and 80 degrees Celsius
respectively.

CONTROL_TSHUT_THRESHOLD[25:16]	- TSHUT_HOT
CONTROL_TSHUT_THRESHOLD[9:0]	- TSHUT_COLD

Change-Id: Ie4263b74038e290ba593155b109d4802660e4243
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
SGX-KM: Add build config for SGX 544 (OMAP 4470)

Adding build config for SGX 544 (OMAP 4470)

Change-Id: Iaecdbd3db551b5685f8d8e3b93656a4b3f33b721
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
HACK: SGX-KM - Bypass OCP for SGX interrupts on 4470

Enable SGX OCP interrupt bypass for 4470. This should
be reverted once a proper fix is in place.

Change-Id: I780b21c619691c9dc8bac780a0b7c8326d613de8
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
SGX-KM: Enable SGX OCP registers for all OMAP4 variants

SGX_OCP_REGS_ENABLED was defined only for SGX 540. This
patch enables OCP registers for OMAP4470 (SGX544) as well.

Change-Id: I1f518a4f01b23786d98b9122c9398fb3468f551e
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
OMAP4: EMIF: Add 4Gb memory Configuration data

Elpida EDB8164B3PF is going to be used on OMAP boards.
Unlike the previous memory this one has two pieces of 4Gb,
so a new configuration stucture should be added.

Change-Id: I98cf8fd2689c21ef7b076aceaf4ed6f7a1b6b0b1
Signed-off-by: Taras Kondratiuk <taras@ti.com>
[Blaze/Tablet] Configure memory for OMAP4470 boards

OMAP4470 SOMs has EDB8164B3PF onboard.
Memory organization is following:
	EMIF1 - CS0 -	4 Gb
	EMIF2 - CS0 -	4 Gb
	--------------------
	TOTAL -		8 Gb

lpddr2_elpida_4G_S4_dev configuration is used.

Change-Id: I2e2dbe4bc386ce903bdcbd6ded624235421df0b0
Signed-off-by: Taras Kondratiuk <taras@ti.com>
HACK: OMAP4470: OPP: Set MPU OPP50 to 396.8MHz

Due to current clock framework implementation we shall prevent unnecessary
matching of DPLL target rate with bypass clock rate.

Otherwise DPLL will be set to bypass mode, that can give unexpected
result.

Example:
	OPP100 -> 0PP50 (assuming that IVA is not holding CORE)
 .---------------------------------------------------------------.
 . _______ _____800MHz_____                                      .
 . |     |                 \                                     .
 . | MPU |                  \______400MHz____                    .
 . |     |                                   \_____200MHz_____   .
 . |-----+-----------------------------------------------------  .
 . |mode | MPU dpll locked | MPU dpll bypass | MPU dpll bypass | .
 . |-----+-----------------------------------------------------  .
 . |     |                                                       .
 . |CORE | _______________400MHz_____________                    .
 . |_____|                                   \_____200MHz_____   .
  ---------------------------------------------------------------
				Result: OPP50 working on 200MHz

To avoid similar situations OPP50 rate will be moved from 400 to 396.8MHz.

Change-Id: I33352aa19506bbdad3cb402c167196471bbf7253
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>