Grab debug information for code ownership.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167933 91177308-0d34-0410-b5e6-96231b3b80d8
s/assert/llvm_unreachable/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167936 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.

When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
Sort the code owner list alphabetically. Add myself as lib/DebugInfo owner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167940 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the largest offender of determinism in BBVectorize

Iterating over the children of each node in the potential vectorization
plan must happen in a deterministic order (because it affects which children
are erased when two children conflict). There was no need for this data
structure to be a map in the first place, so replacing it with a vector
is a small change.

I believe that this was the last remaining instance if iterating over the
elements of a Dense* container where the iteration order could matter.
There are some remaining iterations over std::*map containers where the order
might matter, but so long as the Value* for instructions in a block increase
with the order of the instructions in the block (or decrease) monotonically,
then this will appear to be deterministic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167942 91177308-0d34-0410-b5e6-96231b3b80d8
Claim ownership.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167943 91177308-0d34-0410-b5e6-96231b3b80d8
Fix really stupid ARM EHABI info generation bug: we should not emit
eh table and handler data if there are no landing pads in the function.
Patch by Logan Chien with some cleanups from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167945 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167947 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Implement custom lowering of loads/stores for i1

Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8

Fixes PR13291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
docs: nuke GCCFEBuildInstrs.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167961 91177308-0d34-0410-b5e6-96231b3b80d8
Add myself as code owner for NVPTX target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167962 91177308-0d34-0410-b5e6-96231b3b80d8
The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.

rdar://12028498



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck.rst: change formatting of code-like constructs to use a monospaced
font.  These were formatted in bold, but that's not correct.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167964 91177308-0d34-0410-b5e6-96231b3b80d8
Update my email address and update the code ownership

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167965 91177308-0d34-0410-b5e6-96231b3b80d8
Replace std::vector -> SmallVector in BBVectorize

For now, this uses 8 on-stack elements. I'll need to do some profiling
to see if this is the best number.

Pointed out by Jakob in post-commit review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167966 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes.

The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.

Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.

Effectively reverts r58317. Part of PR2962.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
Remove DOS line endings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167969 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167970 91177308-0d34-0410-b5e6-96231b3b80d8
Added %(line), %(line+<number>), %(line-<number>) substitutions to lit

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