Revert "vidc: Enable error concealment in video core"

This reverts commit d7cf528e9ef94098e800bc02646d2b06d2ffd116.

Change-Id: I1df1cf7833690d50e0362682e51bea1623f57d4f
Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
ASoC: wcd9310: Add the support to instantiate codec driver.

Add the support to instantiate the Codec driver for a given
version of WCD9310 Codec device.

CRs-fixed: 329058
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
(cherry picked from commit cd4b6daee36c5cf0064fe777b4d00cabadbe1c2e)

Change-Id: I2dc8e6d8e19fc85aa82c62fbc49fc3e8d7370b8c
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
ASoC: msm: Add the support to detect the WCD9310 version.

Add support in the machine driver to dynamically detect the WCD9310
version and populate the information to the user space in order to
load the correct UCMs. The default WCD9310 version is 2.0.

CRs-fixed: 329058
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
(cherry picked from commit b25838ef0a9fb5238d456d7971020eb5c56cf9ac)

Change-Id: I11e7a63dbd739b9fd035291174b78b28bb3d7871
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
msm: audio: qdsp6v2: Fix noise issue while SSR

- When SSR is done, we hear an extra noise sound.
- During SSR, Q6 is stopped and AUDIOIF will send the
left over samples in DMA buffers continuously to codec
resulting in noise.
- Disable the active SND devices when SSR is initiated.
This will avoid any noise happening while SSR in progress.

CRs-Fixed: 333915
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
(cherry picked from commit 692c6543452fce8c2104b81cb03fe136e9b1a047)

Change-Id: Id4f63a2ac0f9a8150af23b8c3aa0d5c5935fce2a
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
USB: gadget: u_ether: Fix data stall issue in RNDIS tethering mode

For dual speed gadget, with current no. of request(10), there is
possibility of corner case occurence where all 10 reuqests are queued
to HW without setting IOC bit, which could lead to data stall in
RNDIS tethering and RNDIS local networking.

With this patch, counter will be incremented before queueing request to
HW and sets IOC bit for every nth request due to which the corner case
of all requests queued to HW without IOC bit set will be avoided.

CRs-Fixed: 340995
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
(cherry picked from commit 20b627e58cfdb8172db4315ef823e0d55b45684e)

Change-Id: I7db23f190ec20aa835ab2463b99287be4428fe91
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
mmc: msm_sdcc: reset wait_for_auto_prog_done flag in case of an error

"wait_for_auto_prog_done" flag is set when CMD53, single block write
(CMD24) or pre-defined (prefixed with CMD23) multi block write
(CMD25) need to be sent to card. This flag tells the
msmsdcc_start_data() to set the AUTO_PROG_DONE bit in MCI_DATA_CTL
register. If AUTO_PROG_DONE bit is set, SDCC controller will raise
the PROG_DONE at the end of above mentioned write transfers
(command + data) and "wait_for_auto_prog_done" gets cleared at
the end of transfer.

But if we get the error during the command transfer phase itself,
there is a chance that "wait_for_auto_prog_done" remains set which
means it remains sticky during next SDCC transfer request as well.
And if next data transfer is data read operation, having this
"wait_for_auto_prog_done" flag set will not allow the transfer to
end which may cause SDCC driver to raise request timeout.

Following is one such error condition:
<6>[  667.001892] mmc1: CMD6: Request timeout
<6>[  667.004700] mmc1: SDCC PWR is ON
<6>[  667.007904] mmc1: SDCC clks are ON, MCLK rate=400000
<6>[  667.012848] mmc1: SDCC irq is enabled
<6>[  667.067633] mmc1: SPS mode: busy=0
<6>[  667.071020] mmc1: xfer_size=64, data_xfered=64, xfer_remain=0
<6>[  667.076758] mmc1: got_dataend=1, prog_enable=0,
			wait_for_auto_prog_done=1, got_auto_prog_done=0

This patch ensures that "wait_for_auto_prog_done" gets cleared even when
error is seen during command transfer phase itself.

CRs-fixed: 342901
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
(cherry picked from commit ed6b0e409cbcf15aa8a01ebe9ccefb75548ec912)

Change-Id: I951f6d6bd3bb518a3c047d9c7cf1f3e0fd0dda39
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
slim_msm: Make sure runtime PM reference count doesn't go -ve

Clients may vote for slimbus controller runtime using pm_runtime_get
and pm_runtime_put APIs. Make sure error is logged when client tries
to call pm_runtime_put more than/before pm_runtime_get and it's
not sent to the runtime PM framework to avoid reference count
going -ve.

Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
(cherry picked from commit 38fd18753e66c9d81b1f1234d0f50f74a142704a)

Change-Id: Ibab0392b5f070f9fa54e6df1cfc00d31865696a2
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
Merge branch 'ics_chocolate_rb1' into ics_chocolate

Change-Id: I49b9bbcde519dcb2e948cadbe8f83ad4f9fe3036
Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
msm: pm-8x60: Add clock debug to idle code path.

Clock debug during is suspend is enabled in pm-8x60.
This code has been added to the idle code path to be
able to debug the clocks that are left on and
result in apps not voting for XO during Idle PC.

Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
(cherry picked from commit 6fb932ded7e93dbc42667105dfd461f3c9a86d0e)

Change-Id: I6b5fe6d08d27a85269ee433ce7677b3e6e38557e
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
ASoC: wcd9310: Add the support to instantiate codec driver.

Add the support to instantiate the Codec driver for a given
version of WCD9310 Codec device.

CRs-fixed: 329058

Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
(cherry picked from commit cd4b6daee36c5cf0064fe777b4d00cabadbe1c2e)

Change-Id: I5fd3c7843a15796d08f8617aa1664e3aa7574248
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
ASoC: msm: Add the support to detect the WCD9310 version.

Add support in the machine driver to dynamically detect the WCD9310
version and populate the information to the user space in order to
load the correct UCMs. The default WCD9310 version is 2.0.

CRs-fixed: 329058

Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
(cherry picked from commit b25838ef0a9fb5238d456d7971020eb5c56cf9ac)

Change-Id: I49512bcd8f2b617a68fc30be4af09bbfb1c717cc
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Merge "mmc: msm_sdcc: reset wait_for_auto_prog_done flag in case of an error" into ics_chocolate
Merge "msm: audio: qdsp6v2: Fix noise issue while SSR" into ics_chocolate
Merge "USB: gadget: u_ether: Fix data stall issue in RNDIS tethering mode" into ics_chocolate
Merge changes I11e7a63d,I2dc8e6d8 into ics_chocolate

* changes:
  ASoC: msm: Add the support to detect the WCD9310 version.
  ASoC: wcd9310: Add the support to instantiate codec driver.
Merge "msm: pm-8x60: Add clock debug to idle code path." into ics_chocolate
Merge changes I49512bcd,I5fd3c784 into ics_chocolate

* changes:
  ASoC: msm: Add the support to detect the WCD9310 version.
  ASoC: wcd9310: Add the support to instantiate codec driver.
msm: spm: Do not set the core voltage during driver initilization

The initial voltage value for the cores are setup by bootloaders for
Core 0. The voltages for the secondary cores are set by Core 0 before
bringing them out of reset. When the cores are out of reset, the SAW
regulator takes care of setting core voltage. Thereby we need not set
the voltage for the cores during SPM driver initialization.

Additionally the commit also reorders the SPM register enums to prevent
initiliazation of status registers.

CRs-fixed: 336256
(cherry picked from commit d740fabec659e29ef056faaffa324bfda2c6c97e)

Conflicts:

	arch/arm/mach-msm/board-8064.c

Change-Id: I641c4c2a8e358298d416f778345fb632052b424a
Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: acpuclock-8960: Initialize regulators and bus_bw earlier

The init code assumes that the regulators have already been set
up to support the max CPU frequency. While this is true, the
fewer assumptions we make, the better. So, switch the ordering to
initialize the regulators before switching the frequency. This
also has the nice side-effect of not running the regulators at a
higher than required voltage for fast parts.

While we are at it, also change the bus init ordering so that we
can pick the bus bandwidth that corresponds to the freq the L2
will be initialized to instead of picking the max bandwidth
defined in the bandwidth table.

(cherry picked from commit cfe192bebeb2eaa82b483735e5f8ee5da8c097af)

Change-Id: Ic197d515fb52a25b49c4c2aea32e846bbce9fde2
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Merge changes Ic197d515,Ida2ee603 into ics_chocolate

* changes:
  msm: acpuclock-8960: Initialize regulators and bus_bw earlier
  msm: spm: Do not set the core voltage during driver initilization