OMAP4470: TWL: Set CORE off-mode voltage to 0
OMAP4470: TWL: Set CORE off-mode voltage to 0

Off-mode voltage on CORE domain was increased
to RET voltage by mistake.
Keeping RET voltage on CORE domain during
off-mode increase power consumption up to 0.9 mA.

Change-Id: I260347e18d106d1ba60c35a6ffaebb8d17185e1c
Signed-off-by: Sergii Postulga <x0153364@ti.com>
TUNA: Regulator: Configure VAUX3, VUSIM & VDAC regulators to be disabled in off-mode.
TUNA: Regulator: Set initial state of VDAC regulator
[PATCH] OMAPDSS: DSSCOMP: efficiency improvement.

This change adds 3 local caches of objects, which are used at each flip buffer
action. In original variant kzalloc()/kfree() functions are called each time
dsscomp_gralloc_queue() function is called. This meens that slab|slob|slub
common cache is used at each frame draw action. Call to kzalloc()/kfree()
result in synchronization with other code, which uses common cache, and can
result in dips in FPS, when other code allocates/frees memory.
This change improves reliability, autonomy and efficiency of DSSCOMP module.

Change-Id: Ibf729b922fcd613ff2a2da8e452e0075f5397e55
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAP4: DSS: Implement workaround for Errata ID:i733.

Description of Errata i733:
Due to wrong timings, all register accesses transitioning through the L4
interconnect toward DSS are not reliable.

Workaround:
DSS register access should be addressed through the L3 interconnect.

This change fixes errata by using L3 for access to DSS in dss_hwmod
instead of L4.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4
Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>

Patch Set 5
Revert "OMAP4: PM: IVA AUTO RET relaxed workaround in idle path"

This reverts commit 8af763e77de8776b1e9824f18f63366f4cb681b5.
Revert "Revert "enable c4 state""

This reverts commit 4b0da5ffcb82a7f67de307ba23a2afd661373355.
OMAP4: correct CPU Idle settings for exit latency and thresholds
------------------------------------------------------------------------------------
Cstatesexit_latencythresholds
OMAP4430CPUsMPUCoreususSystemClock
------------------------------------------------------------------------------------
C1WFIONON44ON
------------------------------------------------------------------------------------
C2OFFINAINA300300ON
------------------------------------------------------------------------------------
C3OFFCSWROSWR500010000OFF
------------------------------------------------------------------------------------
C4OFFOSWROSWR520035000OFF
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
Cstatesexit_latencythresholds
OMAP4460CPUsMPUCoreususSystemClock
------------------------------------------------------------------------------------
C1WFIONON44ON
------------------------------------------------------------------------------------
C2OFFINAINA3001800ON
------------------------------------------------------------------------------------
C3OFFCSWROSWR40004000OFF
------------------------------------------------------------------------------------
C4OFFOSWROSWR42004200OFF
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
Cstatesexit_latencythresholds
OMAP4470CPUsMPUCoreususSystemClock
------------------------------------------------------------------------------------
C1WFIONON44ON
------------------------------------------------------------------------------------
C2OFFINAINA5001200ON
------------------------------------------------------------------------------------
C3OFFCSWROSWR53005300OFF
------------------------------------------------------------------------------------
C4OFFOSWROSWR550015000OFF
------------------------------------------------------------------------------------

Change-Id: I6f9046db4273b10cecd7bf896c1a8488774e0d5b
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: PM: fix overconsumption on OFF mode

The wrong value of CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 2 (SW_WKUP)
has been stored in SAR during omap4_sar_save() execution and
causes power over consumption on OFF mode due to C2C operation.
It happens because the L3INIT CD need to be enabled during
omap4_sar_save() execution for proper USBHOST module context storing.

Problematic use case:
1) OMAP goes to sleep,
2) modem wakeup the C2C, the EMIF but the MPU is still sleeping
(as expected)
3) Modem release all his constraints, C2C is turned to OFF.
4) but OMAP never reach again OFF while we don't wakeup the CPU
(by a keypress for example), sys_clk is already ON and voltages
are not equal to 0. (OPP 50 for CORE_3 and retention voltages
for both VCORE1 and VCORE2).

As WA overwrite CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 0x1 (SW_SLEEP).

Change-Id: I2e453c07f61bab28a7213dd66044fd41a021961b
Signed-off-by: Arthur Cassegrain <a-cassegrain@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Patch Set 1