Fixes to the XLP startup code.

Changes are:
- Correct the order of calling init functions.
- Fix up checking excluding reset area.
- use correct mask for chip workaround
Support for XLP4xx and XLP 8xx B0 revision

- Add 4xx processor IDs, add workaround in CPU detection code.
- Update frequency detection code for XLP 8xx
- Add setting device frequency code
- Update processor ID checking code
Interrupt based message handling for XLP B0

Fixup some style issues in the file as well.
Update the L1D cache flush sequence when enabling threads

Added more comments. This code is still experimental.
XLP PCIe code update.

- XLP supports hardware swap for PCIe IO/MEM accesses. Since we
  are in big-endian mode, enable hardware swap and use the normal
  bus space.
- move some printfs to bootverbose, and remove others.
- fix SoC device resource allocation code
- Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL
- some style fixes
Move driver for DS1374 RTC to sys/dev/iicbus

The earlier version of the driver was sys/mips/rmi/dev/iic/ds1374u.c
Simple driver for OpenCores I2C Bus Controller

Polled driver for the OpenCores I2C bus.  This is used
in the Netlogic XLP processors.

Update XLP conf files to use this driver, and provide hints
for i2c devices on XLP engineering boards.

Submitted by:	kanthms at netlogicmicro com (earlier version)
Support for EEPROM and CPLD on XLP EVP boards.

On XLP evaluation platform, the board information is stored
in an I2C eeprom.  The network block configuration is available
from a CPLD connected to the GBU (NOR flash bus). Add support
for both of these.
Remove duplicate entry in XLP.hints
Opencrypto driver for XLP Security and RSA/ECC blocks

Support for the Security and RSA blocks on XLP SoC. Even though
the XLP supports many more algorithms only the ones supported
in OCF have been added.
Submitted by:	Venkatesh J. V. (venkatesh at netlogicmicro com)
xlpge : driver for XLP network accelerator

Features:
- network driver for the four 10G interfaces and two management ports
  on XLP 8xx.
- Support 4xx and 3xx variants of the processor.
- Source code and firmware building for the 16 mips32r2 micro-code engines
  on the Network Accelerator.
- Basic initialization code for Packet ordering Engine.

Submitted by:	Prabhath Raman (prabhath at netlogicmicro com)
		[with some fixups/refactoring by jchandra]
Move UART device to dev/ directory.

Other drivers for the XLP SoC devices will be added here as well
CFI fixes for big endian architectures.

The commands and responses are little-endian which has to be bswapped,
while raw read of data need not be.

Make the default cfi_read and cfi_write do 'htole', and provide a
cfi_read_raw which is used for reading data.
Use DEVMETHOD_END
NOR flash driver for XLP

The NOR interface on the SoC appears on the top level PCI bus. Add
a simple driver for this.
Update memory and resource allocation code for SoC devices

The XLP on-chip devices have PCI headers, but some devices will
need custom resource allocation code.
- devices with no MEM/IO BARs with registers in PCIe extended reg
  space have to be handled in resource allocation
- devices without INTPIN/INTLINE in PCI header can be supported
  by having these faked with a shadow register.
- Some devices does not allow 8/16 bit access to the register space.

Subclass pci and override attach and resource allocation methods to
take care of this.

Remove earlier code which did this partially.
Resource allocation for XLP SoC SDHCI slots

The on-chip SD slots do not have PCI BARs corresponding to them, so
this has to be handled in the custom SoC memory allocation.

Provide memory resource for rids corresponding to BAR 0 and 1 in
the custom allocation code.