Revert "Revert "Ondemand from my omap repository.""

This reverts commit 16ce7c76aae8a3d7e31e0429eb5d07feca17a89c.

Much better results with my OMAP repo version than with stock Ondemand + 2 phase patch.
arm: tegra: pm: Update CPU complex resume

Completely removed PLLP restoration from CPU complex resume on
Tegra2 platforms (too late: PLLP is restored from AVP warm boot
code)

Bug 952200
Bug 931285

Change-Id: I51ca17a943bcbd5753764b4e3c20877519943e27
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/92523
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit 066dc172010f1a5ea5a375e1cbdcf162ab206d63)

ARM: tegra: clock: Update secondary pll dividers resume

During resume from LP0 on Tegra3 always enable pll secondary dividers
before clocks restoration (to make sure clock sources are enabled).
Restore actual secondary dividers settings after clocks are restored.

Remove pllp secondary dividers restoration from cpu complex restore,
and add them to common clock restoration procedure. These dividers
are not affected by CPU complex suspend, only by LP0 core suspend.

Change-Id: I8a09006fad935f8e1cb74c14a87f6246060ba182
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/79938
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 1f631436717c0602ef30770f7976615150114afe)

ARM: tegra: power: Update CPU complex resume

- Completely removed PLLP restoration from CPU complex resume on
Tegra3 platforms (too late: if necessary PLLP is restored by LPx
exit code on Tegra3, and attempt to restore it again does not do
any good).

- Restored PLLX only if it is not already used as CPU source
(it is dangerous to restore PLL in use).

- Restore burst policy on exit from LPx states, but preserve it
after cluster switch, as it maybe different for LP and G clusters.

Change-Id: Ia5ff24d22a2135494bc3442f92bebcc1953c7f08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/72535
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit d278b71cf09fbbdbc9db81427eff0f9053a97b24)

ARM: tegra: Do not flush complete L2 at LP2 entry

There is no need to flush the complete L2 upon LP2
entry. It is sufficient to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.

Bug 931316

Change-Id: I40ce0444e6980147bb499be5cd0abd9907040288
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/85483
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit f474cf90920679789b9612724f1e2cd6dfdbfbbd)
Conflict:
	arch/arm/mach-tegra/pm.c

ARM: tegra: power: Fix warnings when PM_SLEEP is not selected

Change-Id: I88939c92aa1c28f5177010ba2afd524c3a4b713d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/76686
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit 9697b8a6b6445e1aebf8da5ccf343e2fc2b65cdc)

ARM: tegra: power: Fix Tegra2 power timer rate

Commit 0142197cf7b1828fa7935c9d8715f37313864db1 implemented LP0
state entry with fast CPU and system bus clocks only for Tegra3,
but changed power timers rate calculation in the common Tegra2
and Tegra3 path. Fixing it now.

Change-Id: Ib8d5743edda680e9e2658449fe43811549d0603f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/84716
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 9e66d6adf6ab1fe06eee63baf0f1f684715d1ae2)

ARM: tegra: power: Don't lower clocks on LP0 entry

Do not change (lower) CPU and system clocks, and do not disable PLLs
on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway.

Change-Id: I1c9f2f5c0c4259b6c4b0cbed1fcd33ffd7e9231c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83319
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
(cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1)

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Change-Id: Iabbf0785ba7d260c0244fe8b687966b9a16e8d96
Reviewed-on: http://git-master/r/99040
Reviewed-by: Allen Martin <amartin@nvidia.com>