powerpc/p1010rdb: add readme document for p1010rdb

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
powerpc/85xx: minor clean-ups to the P2020DS board header file

Remove some unused macros and remove all #undef macros.

The RTL8139 network adapter is not shipped with the board nor commonly
used, so don't define it by default.  The E1000 is still defined.

Add 57,600 baud as an option.  For some reason, this baud rate is missing
from many boards.

Signed-off-by: Timur Tabi <timur@freescale.com>
powerpc/85xx: fdt_set_phy_handle() should return an error code

fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.

Signed-off-by: Timur Tabi <timur@freescale.com>
powerpc/85xx: clean up P1022DS board configuration header file

Remove some unused default environment variables (memctl_intlv_ctl,
perf_mode, diuregs, dium, and diuerr), update 'tftpflash' variable,
and add videobootargs as a Linux command line variable (so that we can
easily pass video= to the kernel).

Signed-off-by: Timur Tabi <timur@freescale.com>
lib/powerpc: addrmap_phys_to_virt() should return a pointer

addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.

The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/P4080: Check SVR for CPU22 workaround

Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()

We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Workaround for erratum CPU_A011

Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E

Fix SVR checking for commit acf3f8da.

Signed-off-by: York Sun <yorksun@freescale.com>
spi: Tegra2: Seaboard: fix UART corruption during SPI transactions

Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
spi: Tegra2: Seaboard: enable SPI/UART corruption fix

Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: paz00: fix typo in SD slot CD detect GPIO

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: add alternate UART1 funcmux entry

(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: Whistler board support

Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:

E1120 motherboard
E1108 CPU board
E1116 PMU board

The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.

Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: remove some cruft from CONFIG_EXTRA_ENV_SETTINGS

console isn't used by anything, and the kernel should be set appropriately
by whatever script is booting the kernel, not imposed by the bootloader.

mem might be useful, but the current value is pretty bogus, since it
includes nvmem options that make no sense for an upstream kernel, and
equally should not be required for any downstream kernel. Either way, this
is also best left to the kernel boot script.

smpflag isn't used by anything, and again was probably intended to be a
kernel command-line option better set by the kernel boot script.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: flesh out bootcmd

This implements a useful bootcmd for Tegra. The boot order is:

* If USB enabled, USB storage
* Internal MMC (SD card or eMMC)
* If networking is enabled, BOOTP/TFTP

When booting from USB or MMC, the boot script is assumed to be in
partition 1 (although this may be overridden via the rootpart variable),
both ext2 and FAT filesystems are supported, the boot script may exist
in either / or /boot, and the boot script may be named boot.scr.uimg or
boot.scr.

When booting over the network, it is assumed that boot.scr.uimg exists
on the TFTP server. There is less flexibility here since those setting
up network booting are expected to need less hand-holding.

In all cases, it is expected that the initial file loaded is a U-Boot
image containing a script that will load the kernel, load any required
initrd, load any required DTB, and finally bootm the kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: whistler: reduce and comment network cfg options

CONFIG_CMD_PING/NFS aren't required for Whistler to boot.

Add some comments.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: seaboard: add support for USB networking

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: add UART1 on GPU funcmux entry

TrimSlice uses UART1 on the GPU pingroup.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
tegra: sync SDIO1 pingroup enum name with TRM

Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>